Activity

From 08/29/2016 to 09/27/2016

09:26 AM Software Development: RE: Using PREEMPT_RT on MitySOM 5CSX Dev Board: Hello Dan,
I'm now working to create a custom DTS, using socfpga_cyclone5_sockit.dts as a starting point, which in... Jared Kirschner

09:07 AM Software Development: RE: Ethernet not coming up: Yup, tried it with 3 cables (patch, patch and crossover) and 3 devices (switch, router and laptop).
The switch it's ... Michael Ruen

08:25 PM Software Development: RE: Ethernet not coming up: Just out of curiosity, have you tried a different cable? Do you have a switch or anything available to try?
Mos... Michael Williamson
06:00 PM Software Development: RE: Ethernet not coming up: Well it's doing it again. No ethernet. Tried running the gpio test, didn't do anything. When I plug an ethernet cable... Michael Ruen
04:27 PM Software Development: RE: Ethernet not coming up: I'm not sure why it would fail like that, then recover without any real changes. The HPS_GPIO28 controls the Etherne... Adam Dziedzic
12:56 PM Software Development: RE: Ethernet not coming up: I may have fixed it. On the prebuilt image there is the program gpiotest. I ran it just for the heck of it, and here'... Michael Ruen
12:22 PM Software Development: Ethernet not coming up: I turned the board on today with my custom SD image (FPGA, kernel, file structure...) that I have been using the past... Michael Ruen

08:06 AM FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boot: Hi Dan,
Thanks for posting the instructions and looking at the higher resolution operation. This is very useful a... Stephen Snyder

06:21 PM FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boot: Alright, so I was able to get 1080p working. I had to make some changes to the defconfig for the hdmi example. I had ... Daniel Vincelette
10:58 AM FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boot: That's a good idea Mike, it looks like the kernel defaults vram to 4MB but for this framebuffer 8MB+ is required. I'l... Daniel Vincelette

08:21 PM FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boot: Can you up the video ram buffer available for allocation using the kernel parameter of the format below?... Michael Williamson
06:29 PM FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boot: Alright my testing today wasn't as successful as I'd liked. I tried both 1920x1080 and 720x576. Doing 1920x1080 cause... Daniel Vincelette
09:38 AM FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boot: Hi Steve,
I'm testing this now. Hopefully it's just the mods to the device tree/qsys project. I'll update once my ... Daniel Vincelette

08:10 AM FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boot: Hi Daniel,
I saw the project got pushed, thanks.
When do you think you can put together those instructions for ... Stephen Snyder

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Mity CPU Platforms » MitySOM-5CSX Altera Cyclone V