Activity

From 09/04/2016 to 10/03/2016

02:54 PM Software Development: RE: Using PREEMPT_RT on MitySOM 5CSX Dev Board: Hi Dan,
Our hardware engineer just noted a significant difference between two versions of uBootMMCEnv.txt listed o... Jared Kirschner
12:16 PM Software Development: RE: Using PREEMPT_RT on MitySOM 5CSX Dev Board: Hi Dan,
Requested files attached; let me know if I'm missing anything (e.g., FPGA source code).
Also, not sure ... Jared Kirschner
12:04 PM Software Development: RE: Using PREEMPT_RT on MitySOM 5CSX Dev Board: Hi Jared,
Would you mind posting your .qsys file and .dts?
I'll take a quick sanity check,
Thanks
Dan Daniel Vincelette

12:02 PM Software Development: RE: Using PREEMPT_RT on MitySOM 5CSX Dev Board: Addendum: any single PIO (0 through 3) can be enabled in the DTS and the system will boot, but including more than on... Jared Kirschner
08:13 AM Software Development: RE: Using PREEMPT_RT on MitySOM 5CSX Dev Board: Hi Dan,
I did a bit more experimenting with including a subset of the hps_lw_bus sub-nodes. I confirmed with the V... Jared Kirschner

09:13 AM Software Development: RE: Ethernet not coming up: I tested the crystal with an oscilloscope and found the crystal had gone bad. After replacing the crystal everything ... Michael Ruen
12:07 AM Software Development: RE: Ethernet not coming up: Hi Michael,
Sorry for the delayed response.
Would you mind running ethtool and posting the result?... Daniel Vincelette
12:21 AM Software Development: RE: SPI on MitySOM: Hi Brian,
The following device tree uses the SPIM perpherials: http://support.criticallink.com/gitweb/?p=linux-soc... Daniel Vincelette

11:59 PM Software Development: RE: Using PREEMPT_RT on MitySOM 5CSX Dev Board: Hi Jared,
The hps_lw_bus node and all sub nodes are for any FPGA related logic that is attached to the HPS Light w... Daniel Vincelette
04:10 PM Software Development: RE: SPI on MitySOM: dts attached Brian Wentworth
04:06 PM Software Development: SPI on MitySOM: Hi,
I am trying to communicate using the SPIM0 on the HPS with 5CSE-H4-3YA. SPIM0 HPS I/O Set 0 is selected in the... Brian Wentworth

09:26 AM Software Development: RE: Using PREEMPT_RT on MitySOM 5CSX Dev Board: Hello Dan,
I'm now working to create a custom DTS, using socfpga_cyclone5_sockit.dts as a starting point, which in... Jared Kirschner

09:07 AM Software Development: RE: Ethernet not coming up: Yup, tried it with 3 cables (patch, patch and crossover) and 3 devices (switch, router and laptop).
The switch it's ... Michael Ruen

08:25 PM Software Development: RE: Ethernet not coming up: Just out of curiosity, have you tried a different cable? Do you have a switch or anything available to try?
Mos... Michael Williamson
06:00 PM Software Development: RE: Ethernet not coming up: Well it's doing it again. No ethernet. Tried running the gpio test, didn't do anything. When I plug an ethernet cable... Michael Ruen
04:27 PM Software Development: RE: Ethernet not coming up: I'm not sure why it would fail like that, then recover without any real changes. The HPS_GPIO28 controls the Etherne... Adam Dziedzic
12:56 PM Software Development: RE: Ethernet not coming up: I may have fixed it. On the prebuilt image there is the program gpiotest. I ran it just for the heck of it, and here'... Michael Ruen
12:22 PM Software Development: Ethernet not coming up: I turned the board on today with my custom SD image (FPGA, kernel, file structure...) that I have been using the past... Michael Ruen

08:06 AM FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boot: Hi Dan,
Thanks for posting the instructions and looking at the higher resolution operation. This is very useful a... Stephen Snyder

06:21 PM FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boot: Alright, so I was able to get 1080p working. I had to make some changes to the defconfig for the hdmi example. I had ... Daniel Vincelette
10:58 AM FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boot: That's a good idea Mike, it looks like the kernel defaults vram to 4MB but for this framebuffer 8MB+ is required. I'l... Daniel Vincelette

08:21 PM FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boot: Can you up the video ram buffer available for allocation using the kernel parameter of the format below?... Michael Williamson
06:29 PM FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boot: Alright my testing today wasn't as successful as I'd liked. I tried both 1920x1080 and 720x576. Doing 1920x1080 cause... Daniel Vincelette
09:38 AM FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boot: Hi Steve,
I'm testing this now. Hopefully it's just the mods to the device tree/qsys project. I'll update once my ... Daniel Vincelette

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Mity CPU Platforms » MitySOM-5CSX Altera Cyclone V