Mity CPU Platforms » MitySOM-5CSX Altera Cyclone V

02/06/2025

02:27 PM FPGA Development: RE: MitySOM-5csx custom board PL fabric ethernet access

Hi,
It looks like you have a signaltap in your design, which can make it hard to meet timing. I recommend that you... Daniel Vincelette

02:14 PM FPGA Development: RE: MitySOM-5csx custom board PL fabric ethernet access

Hi,
I am facing an issue with new Timing Error in my Project which that generated rbf file, it was not pinging and... Bhardwaj Kotha

01/23/2025

08:40 PM Software Development: RE: MTU increase Issue

What Dan showed you will start your application in the console... if your application exits (or you kill it with ctrl... Tim Iskander

06:55 PM Software Development: RE: MTU increase Issue

Hello,
As Tim said an application launched through cron won't have access to standard in and out. What you could d... Daniel Vincelette

03:17 PM Software Development: RE: MTU increase Issue

Hi,
I am currently working with the MitySOM Cyclone V device, which has only a single UART port. During boot-up, t... Bhardwaj Kotha

01/21/2025

02:09 PM Software Development: RE: MTU increase Issue

If your program is reading from standard input, it will not be able to read anything when launched from cron. cron jo... Tim Iskander

01:03 PM Software Development: RE: Issue with crontab

Hi,
MTU size issue was Resolved, and now I am facing with Crontab.
Actually I am running an application code on b... Bhardwaj Kotha

01:43 PM FPGA Development: RE: MitySOM-5csx custom board PL fabric ethernet access

The Quartus Platform designer adds logic between the AXI bridge (not sure which bridge you are using) and your Avalon... Michael Williamson

01:18 PM FPGA Development: RE: MitySOM-5csx custom board Logic Utilization Issue

Hi,
I am working on Data transmission from HPS to FPGA fabric, So i am used Avalon Memory Interface in Platform De... Bhardwaj Kotha