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Building the QSPI NOR Flash Image 23.1

The MitySOM-5CSx family of modules can boot from, execute code in, and access the on-board Quad-SPI NOR flash. Depending on the module, either 16MiB, 32MiB, 48MiB, or more QSPI NOR memory may be installed. After U-Boot starts, the remainder of the system initialization is application dependent; you may continue to run from NOR by using either a RAM-based filesystem or flash-based filesystems such as JFFS2 or UBIFS.

Note: Modules with more than 16MiB of NOR memory ship with two physical QSPI devices. The device on CS0 is always 16MiB and is the only device that can be used for boot. The device on CS1 adds another 16MiB (or more) that can be accessed once U-Boot is running.

Configuration Requirements

The following items must be configured for a successful NOR boot:
  • Set the BSEL pins to 0x6 (110b) for a 1.8 V device. 0x7 (111b) selects 3.3 V parts and must not be used.
  • Set the CSEL pins to 0x00.
  • Strap the MSEL pins so they match the desired FPGA configuration.
  • Program the preloader at NOR offset 0x0.
  • Program the U-Boot image at the offset chosen in BSP Editor when the preloader was created.
  • On dual-chip modules, keep both the preloader and U-Boot within the first (CS0) device.

Prerequisites

The following files are required:
  • u-boot-with-spl.sfp
  • ubootenv.bin
  • socfpga_mitysom5csx_devkit.dtb (use the DTB that matches your SOM)
  • zImage
  • dev_5cs.rbf
  • initramfs.uImage (RAM Filesystem)

Building the QSPI NOR Flash Image

The layout below reflects the contents needed to boot into Linux. Offsets for most pieces are flexible as long as the U-Boot environment is updated accordingly. The preloader must remain at offset 0x0, and U-Boot must remain at the offset defined while building the preloader/U-Boot pair.

NOR 1 Memory Map

Offset Size File Description
0x00000000 0x00100000 u-boot-with-spl.sfp Four SPL binaries plus U-Boot image
0x00100000 0x00010000 ubootenv.bin U-Boot environment
0x00110000 0x00010000 socfpga_mitysom5csx_devkit.dtb Linux device tree
0x00120000 0x00600000 zImage Linux kernel
0x00720000 <rbf blocks> dev_5cs.rbf FPGA bitstream

NOR 2 Memory Map

Offset Size File Description
0x00000000 0x1000000 RAM filesystem image cpio-based initramfs

Building SPL, U-Boot, and the U-Boot Environment

Ensure the bootloader is built for QSPI by updating the reference project Makefile (for example, mitysom5cs-5csx-ref/dev_5cse_h4_3ya/Makefile):

- 5CS_DEFCONFIG := socfpga_mitysom5cs_defconfig
+ 5CS_DEFCONFIG := socfpga_mitysom5cs_qspi_defconfig

Also update the u-boot enviroment source (software/preloader/uBootMMCEnv.txt.orig):

@@ -1,6 +1,6 @@
 baudrate=115200
 bootargs=console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootwait
-bootcmd=run mmcload; run mmcboot
+bootcmd=run qspiload; run qspiboot
 bootdelay=5
 fpga=0
 fpgaload=bridge disable;fpga load 0 ${loadfpgaaddr} ${loadfpgasize}; bridge enable;
@@ -8,7 +8,7 @@ loadfdtaddr=0x00000100
 loadfpgaaddr=0x2000000
 loadfpgasize=0x700000
 loadinitramfsaddr=0x3000000
-loadkerneladdr=0xA000
+loadkerneladdr=0x100100
 mmcboot=run mmcsetbootargs;run fpgaload;bootz ${loadkerneladdr} - ${loadfdtaddr}
 mmcextpart=3
 mmcfatpart=1
@@ -24,12 +24,12 @@ mmcroot=/dev/mmcblk0p3
 mmcsetbootargs=setenv bootargs console=ttyS0,115200 root=${mmcroot} rw rootwait
 preboot=run setup_usb; ab1805 cs ${rtccal}
 qspiboot=run qspisetbootargs;run fpgaload;bootz ${loadkerneladdr} ${loadinitramfsaddr} ${loadfdtaddr}
-qspifdtloc=0x50000
+qspifdtloc=0x110000
 qspifdtsize=0x6000
-qspifpgaloc=0x8E0000
+qspifpgaloc=0x720000
 qspiinitfsramloc=0x0
 qspiinitfsramsize=0x1000000
-qspikernelloc=0xe0000
+qspikernelloc=0x120000
 qspikernelsize=0x600000
 qspiload=run qspiloadkernel;run qspiloadfdt;run qspiloadfpga;run qspiloadinitramfs
 qspiloadfdt=sf probe 0; sf read ${loadfdtaddr} ${qspifdtloc} ${qspifdtsize}

Build the SPL, U-Boot, and the U-Boot environment from the Quartus reference project:

make uboot
make ubootenv

Building the RAM Filesystem

The RAM filesystem must fit inside the second 16MiB NOR. The core-image-minimal Yocto image satisfies this example. See Building the Filesystem for Yocto setup details. After completing Step 2 of Performing the Yocto Build, build the image:

bitbake core-image-minimal

Add a U-Boot header to the cpio.gz filesystem:

mkimage -n 'Ramdisk Image' -A arm -O linux -T ramdisk -C gzip -d core-image-minimal-mitysom-c5.rootfs.cpio.gz initramfs.uImage

Copy the resulting zImage and DTB (e.g., socfpga_mitysom5csx_devkit.dtb) from Yocto's deploy directory (e.g., tmp/deploy/images/mitysom-c5).

Create the Images that Will Be Programmed into NOR

Gather the following files into a single directory:
  • dev_5cs.rbf
  • initramfs.uImage
  • socfpga_mitysom5csx_devkit.dtb
  • ubootenv.bin
  • u-boot-with-spl.sfp
  • zImage

Create images that mirror the NOR memory maps. These files can then be copied to an SD card for programming via U-Boot.

# Create NOR 1 image (16 MiB)
dd if=/dev/zero of=nor1.img bs=64k count=256
dd if=u-boot-with-spl.sfp of=nor1.img bs=64k seek=0 count=16 conv=notrunc
dd if=ubootenv.bin of=nor1.img bs=64k seek=16 count=1 conv=notrunc
dd if=socfpga_mitysom5csx_devkit.dtb of=nor1.img bs=64k seek=17 count=1 conv=notrunc
dd if=zImage of=nor1.img bs=64k seek=18 conv=notrunc
dd if=dev_5cs.rbf of=nor1.img bs=64k seek=114 conv=notrunc

# Create NOR 2 image (16 MiB)
dd if=/dev/zero of=nor2.img bs=64k count=256
dd if=initramfs.uImage of=nor2.img bs=64k seek=0 conv=notrunc

Reference NOR images

Here are nor images for the 5CSX-H6-42A SOM:

Program via U-Boot

If the carrier board supports an initial boot medium (such as an SD card), you can launch the preloader and U-Boot from SD and program QSPI NOR from the U-Boot prompt:

  1. Place nor1.img and nor2.img on a FAT partition of a bootable SD card.
  2. Interrupt the boot process to reach the U-Boot prompt and load the images from the FAT partition (device 0, partition 1 in this example).
mmc rescan
fatload mmc 0:1 2000000 nor1.img
sf probe 0
sf update 2000000 0 $filesize
fatload mmc 0:1 2000000 nor2.img
sf probe 1
sf update 2000000 0 $filesize

Program via JTAG

If NOR flash is the only boot medium, program the flash before first boot by loading both the preloader and U-Boot over JTAG. Programming via JTAG is considerably slower than the SD-card method.

  1. Connect the USB-Blaster to the HPS JTAG header on the carrier (Drive PX board connector J2 in this example).
  2. Start the Quartus Embedded Command Shell:
    /opt/intelFPGA/18.1/embedded/embedded_command_shell.sh
  3. Program NOR with boot_image.bin at offset 0x0. Use jtagconfig to discover the cable number (assumed to be -c 1 below). Refer to quartus_hps --help for option details.
    quartus_hps -c 1 --operation=P boot_image.bin

Accessing QSPI NOR from Linux

Linux applications can interact with the QSPI NOR devices through the MTD subsystem. Enable the following kernel options:

  • CONFIG_SPI_CADENCE_QSPI
  • CONFIG_MTD_M25P80
    • Requires CONFIG_SPI_MASTER and CONFIG_MTD_SPI_NOR

Define the QSPI partitions in the device tree (for example, in arch/arm/boot/dts/socfpga_mitysom5cs.dtsi within the qspi: spi@ff705000 ...@ node).

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