Activity
From 08/06/2016 to 09/04/2016
09/02/2016
- SS 08:10 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boot
- Hi Daniel,
I saw the project got pushed, thanks.
When do you think you can put together those instructions for updating the resolution?
Thanks a lot,
Steve
08/30/2016
- RF 02:29 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Need Help for Audio MityDSP-L138F. DSP Platforms. No Linux Based
- Hi Bob,
thank you for your respond, hereby I attached my MCASP setup code, I modify the code from evmomapl138. And for schematic I used the schematic that provided by the critical link. I still got nothing from audio output, may be yo...
08/29/2016
- BD 11:27 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Need Help for Audio MityDSP-L138F. DSP Platforms. No Linux Based
- Hi Riyanto,
We don't have a ready-to-go example of setting up the DAC outside of Linux. It's difficult to troubleshoot your problem with the limited details provided.
If you are able to post your initialization/setup code here or...
08/26/2016
- Hello, I'm new using MityDSP, actually I'm moving from evmOMAPL138 to MityDSP.
I generate sine signal then want to play it through DSD1791 DAC so I can hear it. I already set the MCASP but there is no output sound.
I build the progra...
08/24/2016
- DV 09:59 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boot
- Hi Steve,
I'll cleanup and push the project today. I'll also go through and write down what needs to be updated in order to change resolution, I think it will be qsys, device tree, and maybe the initialization code for the HDMI chip b...
08/23/2016
- SS 03:52 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boot
- Hi Dan,
So I'm still not getting any output on my monitors. However, I tried adjusting the monitor settings and I get a message saying out of range signal. I don't understand how I saw the yocto splash screen on this monitor at some... - DV 02:18 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boot
- Sorry about that, it's attached now
- SS 01:41 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boot
- Can you post that image for me to try?
- DV 01:34 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boot
- Awesome, I'll glad it did work on the TV!
I was able to recreate what I think you're seeing on your monitor. If I set my monitor's image size to auto instead of wide then it only showed up as a black screen. When I set it to wide I wa... - SS 12:32 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boot
- Awesome, thanks.
I tried a large screen Samsung HDTV and your latest build works.
I'm hoping that the HDTV's are a bit more forgiving with the back porch value than the monitors, and this latest build works on both.
- DV 12:10 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boot
- Good catch, I'm doing a build now with the those back porch values. I'll let you know when it's finished.
- SS 12:00 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boot
- One thing of note, based on the original qsys file from the wiki page, it seems the back porch values are not the same as those used in the AD9889B programming guide for 720p-60. See attached screenshots. It may be that the display's I...
- SS 11:51 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boot
- No luck, same result, just a black screen.
- DV 11:14 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boot
- Hi Steve,
Attached is a new image. The only thing I changed was that I updated the output delays for the data/control lines to match what the microtronix's example project used. It did work in my dev kit.
Let me know how it goes
...
08/22/2016
- SS 02:10 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boot
- That's ok, thanks for the update Dan. Feel free to post an updated image anytime, even if you don't have a ton of testing. I don't mind being a guinea pig if it gets us to a working example a little bit sooner.
- DV 02:07 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boot
- Steve,
I'm terribly sorry for the radio silence. Unfortunately I've been travelling for the past week so I haven't been able put as much time towards this as I'd like. Thank you for providing the scope captures, the data looks to be p... - SS 07:43 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boot
- Hi Dan,
Any update on this? Have you been able to review the scope shots?
Best,
Steve
08/17/2016
- SS 10:35 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boot
- Hi Dan,
See attached. The index.txt file in the zip package describes each scope shot. Let me know what other measurements I can take.
I've read there is a Quartus reference design for the Microtronix card. Have you compared you...
08/16/2016
- SS 03:35 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boot
- Hi Dan,
Sure thing, I can take these shots first thing in the morning and get them back to you.
Steve - DV 01:12 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boot
- Hi Steve,
Hmm good point that it you've already vetted the monitor you're using. Seeing as you're getting the display to come out of standby and you're boot log didn't have any I2C errors, I'm going to assume the configuration of the ... - SS 07:39 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boot
- Hi Dan,
Thanks for the detail on the I2C fix.
I've tested on two monitors. On one of them, I am certain it supports 1280x720 because I can set it to that resolution when driving it with my PC. Additionally, this monitor is the on... - BW 03:05 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Network Communication MitySOM Custom Kernel Configuration
- Jonathan/Dan,
Solved.... Yes, that was the difference in the two kernels, ipv6 was being built as a module in the custom. Changed to be built into kernel and all works as expected. Thanks for the support.
Brian
08/15/2016
- DV 04:12 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Network Communication MitySOM Custom Kernel Configuration
- Hi Brian,
I've updated the wiki for building the kernel and have added steps for building the modules, it can be found here: https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/Linux_Kernel
The steps at the bottom (... - JC 03:20 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Network Communication MitySOM Custom Kernel Configuration
- Both udp6/tcp6 and '::' points to an error with ipv6 support. Looking at your .config file shows ipv6 being built as a module (CONFIG_IPV6=m). If you either build ipv6 support into your kernel or insert the kernel module and see if thi...
- BW 03:05 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Network Communication MitySOM Custom Kernel Configuration
- Jonathan,
So I built a new kernel setting the base configuration as mitysom5csx_devkit_defconfig without doing the menuconfig and building the uImage. Then I added that uImage to the /boot folder in the rootfs that is on the SD image ... - DV 03:11 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boot
- Hi Steve,
Sorry for the delay, I was travelling Friday afternoon.
To fix for the I2C issue was that I resampled and debounced the I2C signals coming into the FPGA before feeding them to the HPS I2C master. I expected the HPS to ta... - SS 10:45 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boot
- Hi Dan,
This image doesn't show anything on my monitor. Upon first booting it, right after the console printed "Setting Up HDMI Transmitter", the monitor came out of standby but the screen stayed black. After powering the system off...
08/12/2016
- BW 03:27 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Network Communication MitySOM Custom Kernel Configuration
- I have both the L2_3Y8 and H4_3YA.. Attached is the config file for my 3YA. Dont think it really matters. Both error with the Firefox COAP.
Thanks for the help,
Brian - JC 02:25 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Network Communication MitySOM Custom Kernel Configuration
- Can you post your .config file?
Thanks
Jonathan Cormier - Hello,
I have a MitySOM dev board with the 5CSE-H4-3YA. I am able to use the pre-built binary SD card image for network communication using Firefox Copper with udp COAP packets. The program has no problem identifying the host IP infor... - SS 12:15 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boot
- Hi Dan
Thanks for this. I can try the image on Monday and report back results.
Can you provide a little detail on the fix? Alternately if it is in Git (or will be there shortly), I can just look at the commit.
Best,
Steve - DV 11:56 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boot
- Hello Steve,
I've created an alpha SD card image that from my testing has fixed the i2c failures. The filesystem also now has X11 and launches XFCE on boot (if you have a USB OTG cable a mouse/keyboard can be used)
The image should...
08/11/2016
- JK 10:05 AM MitySOM-5CSX Altera Cyclone V Software Development: RE: Using PREEMPT_RT on MitySOM 5CSX Dev Board
- Hi Dan,
The network stability problem has disappeared after removing the skews. Thanks for the suggestion!
I'll soon proceed with additional defconfig/dts modifications, starting with the suggestions above.
Thanks,
Jared
08/10/2016
- DV 11:12 AM MitySOM-5CSX Altera Cyclone V Software Development: RE: Using PREEMPT_RT on MitySOM 5CSX Dev Board
- Hi Jared,
Looking at the sockit dts(https://github.com/altera-opensource/linux-socfpga/blob/socfpga-4.1.22-ltsi-rt/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts) I see they are setting skews for the data clocks for the RGMII phy. We d... - JK 10:38 AM MitySOM-5CSX Altera Cyclone V Software Development: RE: Using PREEMPT_RT on MitySOM 5CSX Dev Board
- Hello Dan,
I've been performing more testing on the Altera 4.1.22 LTSI RT branch.
Physical setup: MitySOM 5CSX H6 HYA dev kit connected to network via Ethernet (J500).
Altera 4.1.22 LTSI RT does indeed get an IP address, but the...
08/09/2016
- DV 10:30 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boot
- Hello Steve,
There was a bit of stability issue with the I2C interface to the HDMI transmitter IC. I thought my newest build of the demo had the stability issue ironed out though, let me take try it here again and I'll post back with ... - Hello,
I'm trying to run the HDMI output image provided on the wiki. I haven't modified anything just written the image to an SD card.
When booting, the splash screen sometimes shows up, but usually doesn't. I'm also intermittent... - DV 10:24 AM MitySOM-5CSX Altera Cyclone V Software Development: RE: Using PREEMPT_RT on MitySOM 5CSX Dev Board
- Hi Jared,
Glad to hear that worked for you! If you run into trouble getting your defconfig/dts setup how you want just let me know.
Dan - JK 09:40 AM MitySOM-5CSX Altera Cyclone V Software Development: RE: Using PREEMPT_RT on MitySOM 5CSX Dev Board
- Hello Dan,
Thanks for pushing the dizzy (1.7) branch. I've successfully gotten to the same point you did in your first reply via a Yocto build (Altera Linux 4.1.22 LTSI RT is booting and receiving an IP address, but still need to modi...