Mity CPU Platforms

07/22/2019

01:34 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Change data between ARM(Linux) - DSP (bare-metal)

Aviv Prital wrote:
> Hi, thanks for reply!
> Two follow up questions:
> Concerning "you may want to look at some o... Jonathan Cormier

07/18/2019

06:00 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Change data between ARM(Linux) - DSP (bare-metal)

Hi, thanks for reply!
Two follow up questions:
Concerning "you may want to look at some of the DSPlink or syslink c... Aviv Prital

07/17/2019

03:04 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Change data between ARM(Linux) - DSP (bare-metal)

Note if your writing your own bare-metal communication you may want to look at some of the DSPlink or syslink code as... Jonathan Cormier

02:05 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Change data between ARM(Linux) - DSP (bare-metal)

Thanks for the prompt reply!
I'm thinking about shared RAM that ARM user space linux driver will be able to mmap in ... Aviv Prital

02:01 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Change data between ARM(Linux) - DSP (bare-metal)

Could you provide more information on what is suitable for your project? Jonathan Cormier

01:44 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: Change data between ARM(Linux) - DSP (bare-metal)

Hi,
I'd like to use MityDSPL138 kit in order to develop ARM(Linux) - DSP (bare-metal) data exchange over shared memo... Aviv Prital

07/08/2019

02:57 PM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: Reference Project AnalogExpansionSuite query

Hi,
I have a custom board with
-- MityDspl-138F module (with FPGA)
-- No Ethernet port
-- UART,USB,SD CARD int... Vivek Ponnani

10:05 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uPP receive clock lower limitation in SDR (Single Data Rate mode)

Thanks Greg for your reply and sorry for the late reply.
I will forward your response to our FPGA team. They are u... Vivek Ponnani

07/03/2019

11:04 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Set timing constraints

Hi Davide,
You really need a constraints file for this to constrain the input timing signals properly based on the... Michael Williamson

09:20 AM MitySOM-5CSX Altera Cyclone V FPGA Development: Set timing constraints

Dear all,
I have a MitySOM 5CSX-H6-4YA with a Cyclone V SoC installed on a custom board with ADCs and DACs. What I... Davide Vaccaro