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MF 05:15 PM MitySOM-A5 FPGA Development: RE: PCIe Root Port bring-up on MitySOM-A5E (A5ED-B64-144-SRC-X) — hard system hang, likely missing GTS reset sequencer for right-side bank

Hi Brady,
Thanks for the details. Both of your fixes look correct and I think you're one step from the real problem (which you pointed out).
You moved the PCIe IP from the left shoreline bank to the right shoreline bank (the FMC), ... Mike Fiorenza

MF 03:23 PM MitySOM-A5 FPGA Development: RE: Programming File Generation

Max,
Did you try clicking the Generate button? I think the GUI is just bugged stating that the SOF doesn't have the bootloader, however, your pfg file properly declares the bootloader path. Once I clicked generate it merged the SOF wi... Mike Fiorenza

08/20/2026

MK 07:33 PM MitySOM-A5 FPGA Development: Programming File Generation

Hello Sir/Madam,
I'm trying to create Programming File Generator for our own project based on your example design. Your eaxample design uses Makefile that build, compile and generate programming Files. We have our own scripts to build... Maxim Kanevsky

BH 07:21 PM MitySOM-A5 FPGA Development: PCIe Root Port bring-up on MitySOM-A5E (A5ED-B64-144-SRC-X) — hard system hang, likely missing GTS reset sequencer for right-side bank

Subject: PCIe Root Port bring-up on MitySOM-A5E (A5ED-B64-144-SRC-X) — hard system hang, likely missing GTS reset sequencer for right-side bank
Setup:
Board: MitySOM-A5E, part A5ED-B64-144-SRC-X, mitysom-a5e-ref-base project, pro_2... Brady Heater

DC 06:29 PM MitySOM-QC6490 Software Development: RE: Adreno GPU userspace: newer OpenCL driver (cl_qcom_ml_ops)? + headless Vulkan notes

Hi Greg,
Fantastic — thank you. A preliminary QLI 2.0 build would be very welcome. The interfaces we need functional, in priority order:
*Must-have (our current working paths — regression-sensitive):*
# OpenCL 3.0 on the Adreno 64... David Cuccia

08/19/2026

GG 11:15 PM MitySOM-QC6490 Software Development: RE: Adreno GPU userspace: newer OpenCL driver (cl_qcom_ml_ops)? + headless Vulkan notes

Hi David,
Regarding Item 1:
We are currently working on support for for QLI 2.0 as our next release. Below is a table my buddy Opus created based our current release and some internal WIP updates we have:
| | QLI 1.5 | QLI 1.6 ... Gregory Gluszek

08/17/2026

DC 09:09 PM MitySOM-QC6490 Software Development: Adreno GPU userspace: newer OpenCL driver (cl_qcom_ml_ops)? + headless Vulkan notes

Hi Critical Link team,
We are evaluating the MitySOM-QCS6490 for a medical imaging product. I've been able to get up and running with the dev kit and I'm experimenting with FP32 ML inference on the Adreno 643 GPU (headless, containeri... David Cuccia

JC 05:35 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: AM62A: Getting the Splash Screen to Appear Earlier

AM62A splashscreen changes have been merged into https://support.criticallink.com/gitweb/?p=u-boot-ti.git;a=shortlog;h=refs/heads/mitysom-u-boot-2025.01 Jonathan Cormier

08/14/2026

MF 07:12 PM MitySOM-A5 PCB Development: RE: MitySOM Standard Carrier Board FMC pin assignment typo

Hi Max,
I reviewed your pinout and it looks correct to me.
One thing to mention is that I have posted our FMC example design and Wiki page here: [[A5E-FMC-Example]]. You obviously don't need to use this example design as you presum... Mike Fiorenza

MK 05:33 PM MitySOM-A5 PCB Development: RE: MitySOM Standard Carrier Board FMC pin assignment typo

Hello Mike, thank you so much for your help!!!
I'va attached my pin assignment table with fixes. Can you please take a look and see if exerything is correct. Meanwhile, I'll try to compile with these modifications.
Thanks,
Max Maxim Kanevsky

MF 05:20 PM MitySOM-A5 PCB Development: RE: MitySOM Standard Carrier Board FMC pin assignment typo

Hi Max,
You are correct, it is a typo in the FPGA Pin column and not a board issue. Both nets route correctly on the carrier and on the SoM.
Your D12 row is the good one:
* D12 (LA05_N), HVIO route: SoM pin J1-C12, HVIO_6A_12, F... Mike Fiorenza

MK 04:29 PM MitySOM-A5 PCB Development: RE: MitySOM Standard Carrier Board FMC pin assignment typo

In addition to previous message, pin H8 also doesn't seems to be right connection (VR31) Maxim Kanevsky

MK 03:44 PM MitySOM-A5 PCB Development: MitySOM Standard Carrier Board FMC pin assignment typo

Hello dear Sir/Madam,
I found some small typo in document: MitySOM-A5E-Standard-Development-Kit-Datasheet.pdf (inside document: 60-000098 Rev 1A):
- in table Table 17: J3 Connector Pin Assignments, pin C10 assigned to FPGA Pin: BR22
... Maxim Kanevsky

BD 06:20 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Yocto build support

Fred,
TI's latest SDK for the MityDSP-L138 processor was released in April 2020. This TI release was based on Yocto Thud.
Any kernel or application vulnerabilities since then would need to be disabled in the kernel or would need t... Bob Duke

08/13/2026

MF 02:43 PM MitySOM-A5 FPGA Development: RE: PCIE_RP example design - IPs question

Eleonora,
Thanks for the details. The short answer is that make jic is most likely building from the cores you edited. The Makefile make jic flow is essentially the same as hitting the compile button in Quartus, just with an extra ass... Mike Fiorenza

EH 01:41 PM MitySOM-A5 FPGA Development: PCIE_RP example design - IPs question

Good morning,
I'm still trying to run the PCIe_RP example design. As we have discovered, the device that is on the board is not the one that the project was generated for, so when I changed the device Quartus needed me to update the cor... Eleonora Haralanova

08/07/2026

FW 03:00 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Yocto build support

I also looked into TI Yocto support for the L138 (meta-ti, Arago?). AI indicated they stopped support about 2017 (Morty?). As you have more inroads with TI than me or AI, can you confirm this? What is the latest Yocto/Kernel supported by... Fred weiser

08/06/2026

MK 06:31 PM MitySOM-A5 FPGA Development: RE: HPS to FPGA Manager (Memory-Mapped) question

Hello Mike,
Thanks a lot for your reply.
We used this offset 0x4000_0000 (1 GB) and we got the expected reply from/to our registers!!!
Thanks for your refferal to memtool. We tested memtool, but need our application as well.
Than... Maxim Kanevsky

MF 06:08 PM MitySOM-A5 FPGA Development: RE: HPS to FPGA Manager (Memory-Mapped) question

Hi Maxim,
Thanks for sending the project along, that made this much easier to answer.
*On fpgaregister.h.* Yes, it works for the full HPS to FPGA bridge. There is nothing in that header that is specific to the Lightweight bridge, i... Mike Fiorenza

MK 04:56 PM MitySOM-A5 FPGA Development: HPS to FPGA Manager (Memory-Mapped) question

Hello dear Sir/Madam!!!!
we have again some question.
Based on your A5ED-B64-144-SRC-X/mitysom-a5e-ref-dma Example Desigmn, we added custom DMA Loopback (this is already working for us) and additional HPS to FPGA Manager 64 bit Data,... Maxim Kanevsky

08/03/2026

BD 07:20 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Yocto build support

Hello Fred,
I don't have an easy answer here. Our latest release, available under the files tab, is from April 2018. Our public @meta-mitydsp-l138@ is here: https://support.criticallink.com/gitweb/?p=meta-mitydsp-l138.git;a=summary.
... Bob Duke

FW 06:09 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: Yocto build support

We have been building the ARM9 code using Yocto (daisy). Do you have public facing meta layer support? (meta-criticallink and meta-mitydsp-l138) What is the latest Yocto version supported by Critical Link for the L138? Cybersecurity requ... Fred weiser

07/30/2026

MF 02:46 PM MitySOM-A5 FPGA Development: RE: Custom Loopback based on mSG-DMA Example Design

Max,
Glad to hear you have it working!
After giving this another thought, my guess may be that your FPGA design may still have been based off my previous FPGA design example. Then when I posted the new release, you may have just ta... Mike Fiorenza

MK 02:32 PM MitySOM-A5 FPGA Development: RE: Custom Loopback based on mSG-DMA Example Design

Hello Mike,
Thanks a lot for your help.
I've implemented all the points you've mentioned.
This is very strange, I don't understand how this happened that SMMU was disabled and A5E Cache Coherency and DMA's had different setting than... Maxim Kanevsky

07/29/2026

DK 09:30 AM MitySOM-A5 FPGA Development: RE: Custom Loopback based on mSG-DMA Example Design

> First things first: our example design is not a loopback.
> ...
It was understood after analyzing the example C code. But the first Visio picture is taken directly from documentation. Please update it.
Dmitry Kirilin

07/28/2026

MF 09:57 PM MitySOM-A5 FPGA Development: RE: Custom Loopback based on mSG-DMA Example Design

Hi Maxim,
Thanks for the detailed write-up, and thanks especially for attaching the archive. I pulled your project apart and diffed it against our reference design, and I think I found your problem. Let me answer your example design q... Mike Fiorenza

MK 07:33 PM MitySOM-A5 FPGA Development: Custom Loopback based on mSG-DMA Example Design

Dear Sir/Madam,
We are using your mSG-DMA Example Design and trying to make our custom Loopback based on this example design.
Please see attached to this message PDF file with drawings of Example Design and our Custom Loopback based ... Maxim Kanevsky