Activity

From 05/03/2026 to 06/01/2026

03:31 PM Software Development: RE: cl_msgdma.ko has the wrong version: Hi Samuel,
We plan to integrate this kernel module into our kernel in the near future, so this would be handled au... Mike Fiorenza

10:03 PM Software Development: RE: cl_msgdma.ko has the wrong version: This way works to make a compatible version of cl_msgdma.ko. (/) :D
Is there a way to build it inside the docker ... Samuel Paul
07:28 PM Software Development: RE: cl_msgdma.ko has the wrong version: Hi Samuel,
The Wiki instructions say to deploy the compiled kernel and kernel modules to the SD card as well. This... Mike Fiorenza
06:55 PM Software Development: cl_msgdma.ko has the wrong version: When I try to insert the cl_msgdma kernel module I get the following message.
root@mity-a5e:~# insmod cl_msgdma.ko... Samuel Paul

03:43 PM Software Development: RE: make_sd.sh doesn't take command line parameters: Hi Max,
As mentioned in the "HPS/FPGA Shared Memory thread":https://support.criticallink.com/redmine/boards/75/top... Mike Fiorenza
03:32 PM Software Development: RE: make_sd.sh doesn't take command line parameters: Hello Zach,
We are back to test DMA example design.
Do you have any update regarding the failure that we saw??
... Maxim Kanevsky

02:44 PM FPGA Development: RE: HPS/FPGA shared external memory: Hi Max,
Just to make sure we're aligned on the DMA example — what it demonstrates is really the same use case you'... Mike Fiorenza
01:42 PM FPGA Development: RE: HPS/FPGA shared external memory: Sorry, forgot to mention, as you suggested, ve tried first DMA example design and we tried to run it. But for now we ... Maxim Kanevsky
01:40 PM FPGA Development: RE: HPS/FPGA shared external memory: Hello again,
I've created a project based on mitysom-a5e-ref-base project.
We made following modifications:
- we... Maxim Kanevsky

05:09 PM PCB Development: RE: HVIO Speed at 3v3: Hi Naufal,
The "Agilex-5 datasheet":https://docs.altera.com/r/docs/813918/current/agilextm-5-fpgas-and-socs-device... Michael Williamson
04:45 PM PCB Development: HVIO Speed at 3v3: Hello,
I'm working on an FMC PCB that will interface with the MitySBC-A5E. The board contains an ADV7611 HDMI rece... Naufal Ahmad

06:20 PM FPGA Development: RE: Signal Tap not working: Hello Mike, thanks a lot. Yes, not it is working
Max Maxim Kanevsky
04:51 PM FPGA Development: RE: Signal Tap not working: Hi Max,
As shown on the right side of your screenshot, you do not have the correct device selected. You need to se... Mike Fiorenza
04:40 PM FPGA Development: Signal Tap not working: Hello !!!
We are using mitysom-a5e-ref-base as a reference and we've added FPGA2SDRAM port to HPS and some Avalon Me... Maxim Kanevsky

10:38 PM Software Development: RE: How to make usb to ethernet work ?: Thanks Mike
Now I have 3 ip devices (including the usb/ethernet on usb-c)
root@mity-a5e:~# ip addr
1: lo: <LOO... Samuel Paul
09:20 PM Software Development: RE: How to make usb to ethernet work ?: Hi Samuel,
To use a USB-to-Ethernet adapter, the Linux kernel needs to include the appropriate USB networking driv... Mike Fiorenza
07:33 PM Software Development: How to make usb to ethernet work ?: I am working with Maxim on the same machine.
We would like be able to make usb to ethernet adapter work. Samuel Paul
09:09 PM FPGA Development: RE: HPS/FPGA shared external memory: Hello Mike,
Thanks a lot for your answer. I've found the same after I posted the question...
Thanks,
Max Maxim Kanevsky
08:55 PM FPGA Development: RE: HPS/FPGA shared external memory: Hi Max,
Yes, this is possible on the Agilex 5 platform, but the external memory connected to the HPS EMIF is not i... Mike Fiorenza
04:28 PM FPGA Development: HPS/FPGA shared external memory: Dear Sir/Madame,
I would like to create my own design based on mitysom-a5e-ref-base, but with shared between HPS/F... Maxim Kanevsky

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