Mity CPU Platforms » MitySOM-A5

05/19/2026

03:43 PM Software Development: RE: make_sd.sh doesn't take command line parameters

Hi Max,
As mentioned in the "HPS/FPGA Shared Memory thread":https://support.criticallink.com/redmine/boards/75/top... Mike Fiorenza

03:32 PM Software Development: RE: make_sd.sh doesn't take command line parameters

Hello Zach,
We are back to test DMA example design.
Do you have any update regarding the failure that we saw??
... Maxim Kanevsky

05/14/2026

02:44 PM FPGA Development: RE: HPS/FPGA shared external memory

Hi Max,
Just to make sure we're aligned on the DMA example — what it demonstrates is really the same use case you'... Mike Fiorenza

01:42 PM FPGA Development: RE: HPS/FPGA shared external memory

Sorry, forgot to mention, as you suggested, ve tried first DMA example design and we tried to run it. But for now we ... Maxim Kanevsky

01:40 PM FPGA Development: RE: HPS/FPGA shared external memory

Hello again,
I've created a project based on mitysom-a5e-ref-base project.
We made following modifications:
- we... Maxim Kanevsky

05/12/2026

05:09 PM PCB Development: RE: HVIO Speed at 3v3

Hi Naufal,
The "Agilex-5 datasheet":https://docs.altera.com/r/docs/813918/current/agilextm-5-fpgas-and-socs-device... Michael Williamson

04:45 PM PCB Development: HVIO Speed at 3v3

Hello,
I'm working on an FMC PCB that will interface with the MitySBC-A5E. The board contains an ADV7611 HDMI rece... Naufal Ahmad

05/11/2026

06:20 PM FPGA Development: RE: Signal Tap not working

Hello Mike, thanks a lot. Yes, not it is working
Max Maxim Kanevsky

04:51 PM FPGA Development: RE: Signal Tap not working

Hi Max,
As shown on the right side of your screenshot, you do not have the correct device selected. You need to se... Mike Fiorenza

04:40 PM FPGA Development: Signal Tap not working

Hello !!!
We are using mitysom-a5e-ref-base as a reference and we've added FPGA2SDRAM port to HPS and some Avalon Me... Maxim Kanevsky