Mity CPU Platforms » MityDSP-L138 (ARM9 Based Platforms)

Hi,

So currently the DspGpio.cpp implementation (for non-FPGA GPIO's) for the 674X core is does not implement interrupt handling (see the tcDspGpio::ConfigurePin() method in the source code). However, support could be added without too much effort if you are comfortable with basic DSP/BIOS interrupts. There are four things that need to be done:

1) Configure the DSP Event Map using HWI_eventMap() to route the GPIO interrupt levels to one of the available DSP core interrupt lines. Don't use levels 3-5 as they are reserved for DSPLINK, and don't use the level you are using for FPGA interrupts if you are using an FPGA based module or IP.

2) Add an interrupt handler using HWI_dispatchPlug().

3) make sure that the interrupt conditions (rising or falling edge) are enabled for the GPIO pin of interest. You'll need to check the OMAP-L138 TRM for details on this. Basically there is a register mask to write to set interrupt or clear interrupt sensitivity for rising or falling edges.

3) Enable the interrupt.

If you look in the DspIntDispatch.cpp file in the register_isr_callback() method, this is done for the 2 GPIO pins, Bank 6 Offsets 12 and 13, used to route interrupt conditions from the FPGA cores to the OMAP-L138.

I'm sorry for the inconvenience, we should really add support for this in the library. The real issue is that there is a very limited number of interrupts available on the DSP core, and we didn't want to tie up any more than was necessary up.

If you get stuck, please follow up on this thread, we should be able to help you along.

-Mike

Hello again,
First of all,thank you for your quick reply.

I am trying to implement the solution focusing on your advices. So far, it is not working. Here is what I did.
From the beginning:

1) Configuring the DSP Event Map:
I invoked function:
HWI_eventMap(6, 10);
The first parameter was clear to me- I used 6 by which I understand is a level 6- HWI_INT6 from the .tcf file, curretly unused. However, I am not quite sure what the second parameter- in various projects I found different numbers- tcDspIntDispatch.cpp the second parameter was used 62, but I don'd know how (and whether or not) it is calculated:
const unsigned int GPIO_B6INT = 62;

2) Adding an interrupt handler:
I invoked the method HWI_dispatchPlug and declared the handler:

void HandleInterrupt(void) {
return;
}

HWI_dispatchPlug(6, (Fxn)HandleInterrupt, -1, NULL);

The last parameter was NULL- the same as in implementation in DspVpif.cpp, so this rather should work.

3) adjusting the interrupt conditions (rising or falling edge) in the register:
I focused on the OMAPL138 TRM- http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
On page 905 (chapter 21.2.10.3) is the instruction how to enable the interrupts- apparently in my case to enable rising-edge interrupts I should set GP0P1 (that is least-but-one significant bit of the register) of SET_RIS_TRIG01 to 1 and set GP0P1 of CLR_RIS_TRIG01 to 0. I tried to do this in debug mode, but unfortunately when I set any value in SET_RIS_TRIG01 to 1 the same bit was automatically set in CLR_RIS_TRIG01.
As a second try I tried to make do with the example code from your version of StarterWare. what I did was a bit complicated, so let me describe it thoroughly: * I copy-pasted into my project the declaration and definition of method:

  void GPIOIntTypeSet(unsigned int baseAdd, unsigned int pinNumber,
                    unsigned int intType);

Which I subsequently invoked as:

  GPIOIntTypeSet(SOC_GPIO_0_REGS, 2, GPIO_INT_TYPE_RISEDGE);

The second argument is used to set a SET_RIS_TRIG01 register to 1. I figured out it is calculated the following way: {bank_no}*{16+offset}+1, so in my case it was 2: 0*16+1+1 * I attached the following header files to my project from the StarterWare gpio project: hw_gpio.h gpio.h, hw_types.h, soc_OMAPL138.h and subsequently added the following includes in my source code:

  #include "gpio.h" 
  #include "hw_types.h" 
  #include "soc_OMAPL138.h" 

However, I have the same problem- the bit of CLR_RIS_TRIG01 is automatically set to 1 if I set the corresponding bit of SET_RIS_TRIG01

3) Enabling the interrupt:
I invoked the method for previously chosen level 6
C62_enableIER(1 << 6);

If you have any idea what is wrong, any help is invariably very welcome.
Best regards
Rafal Krawczyk

A little corrction in what I have written in my previous mail- for bank 0 offset 0 (J701 pin 25) the function call shlould be: GPIOIntTypeSet(SOC_GPIO_0_REGS, 1, GPIO_INT_TYPE_RISEDGE): 16*0 +0 +1 . Still, it is not working.

Best regards
Rafal Krawczyk

For the DSP Event Map (item number 1), refer to table 3-1 of the TRM in section 3.2.2.1.

GPIO Bank zero event appears to be 65. Looks like there is only one interrupt per bank.

For 2, check DspFirmware.cpp on how to set for rising edge (use the right bank numner). Be careful, a lot of those registers can be write only, so their readback status can be deceiving.

I think if you fix up the EventMap call, you may have some success....

-Mike

Hello again,
It works ! Invoking EventMap with an appropriate second argument solved the problem:
HWI_eventMap(6, 65);
Thank you very much.

Best regards
Rafal Krawczyk

I have some follow-on questions for this thread, because this is something I am working on right now (DSP/BIOS non-FPGA GPIO interrupts. My questions are:

1. re pinmux - according to the Industrial I/O schematic, it appears that many pins in Bank 0 are already set up as GPIO, for example 0,1,2,3,4,5,6,13, 15. Is that correct?
2. Re interrupt mapping - in Setting up interrupts in DSP/BIOS http://processors.wiki.ti.com/index.php/Setting_up_interrupts_in_DSP_BIOS

using the Scheduling-HWI module takes care of the interrupt vector table, interrupt event mapping, global interrupt enable, and interrupt nesting (if desired)

So as I see it what I have to do is configure the pin to interrupt the way I want it, write the interrupt handler, and enable the interrupt.

Am I right?

Hello Steven,

1. It is highly recommended to set the pins up in a matter you want to use them. The processor may be configured at a startup to have these pins as GPIO's, but this configuration can be changed by the other application, so the safest way is to configure the pins at the start of DSP application, just in case. However, if you want to check, what is the configuration of pins, the answer might be in the OMAPL138 TRM- http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf

2. Basically, yes. Should you focus on this thread's earlier messages, you will find how to implement this configuration.

Best regards,