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Call to tcDspFpgaGpio::ConfigurePin() makes the Dsp crash
Added by Michele Canepa almost 11 years ago
Dear Sirs,
I have to use a GPIO bank over FPGA to route some interrupts (let's say 8) through the fpga to the DSP.
For the purpose, I have used the call to tcDspFpgaGpio::ConfigurePin() method and subsequently SetISRCallback() method to hook the ISR to the GPIO event.
Everything worked fine for the first two GPIOs, Bank:0 Offset:0 and Bank:1 Offset:1, I could setup interrupt and see them arriving smoothly without problems.
Something strange happened when I try to configure the third pin, Bank:0 Offset:2: this call makes the DSP crash and I have to reset the EVM.
I post the code snippet for both C side and VHDL:
DSP SIDE: inside the init task
@void init()
{
// Buffer for return message
char lpReturnMessage256;
//======== DSPLINK buffer ===========================
// Create the outbound debug link
gpDebug = new tcCL_IPCOutbound("debug");
// Create the inbound link for messages to the DSP
gpInbound = new tcCL_IPCInbound();
gpInbound->Open("DSPMSGQ0", 8);
if (NULL != gpInbound)
{
// Register a callback function to handle messages from the ARM
gpInbound->RegisterCallback(handleInboundMessage, (void*)NULL);
}
// Create the outbound controller for sending messages to the ARM
gpOutbound = new tcCL_IPCOutbound("GPPMSGQ1");
//Fpga firmware initialization
tcDspFirmware::set_firmware_base((void*)FPGA_BASE_ADDR); //This is the base address of FPGA
int r1 = tcDspInterruptDispatch::set_hw_interrupt_level(0,10);
//End of frame core initialization
tcDspFpgaGpio Eof0 = new tcDspFpgaGpio((void)0x66000080);
int rconf0=Eof0->ConfigurePin(0,0,0,0,true,false);
int rconf1=Eof0->ConfigurePin(0,1,0,0,true,false); //Until this line everything works fine !! <----------
//Eof0->ConfigurePin(0,2,0,0,true,false); //This line makes the dsp crash...<-------
//Eof0->ConfigurePin(0,3,0,0,true,false);@
int isrconf0= Eof0->SetISRCallback(0,0,MyISR0,NULL);
int isrconf1=Eof0->SetISRCallback(0,1,MyISR0,NULL);
//isrconf0= Eof0->SetISRCallback(0,2,MyISR0,NULL);
//isrconf1=Eof0->SetISRCallback(0,3,MyISR0,NULL);@VHDL snippet for the instantiation if the FPGA GPIO core.
Definitions:
-- 0x6600 0080
constant CORE_INT_EOF: integer:=1;
constant CORE_INT_EOF_LEVEL : integer := 0;
constant CORE_INT_EOF_VECTOR: integer := 0;
Instantiation of the core.
-----------------------------------------------------------------------------
-- GPIO: Interrupt for end of frame
-----------------------------------------------------------------------------
int_eof: gpio
generic map(
NUM_BANKS =>1,
NUM_IO_PER_BANK=>16)
PORT MAP(
clk => ema_clk,
i_ABus => addr_r,
i_DBus => edi_r,
o_DBus => edo_arm(CORE_INT_EOF),
i_wr_en => wr_r,
i_rd_en => rd_r,
i_cs => arm_cs5_r(CORE_INT_EOF),
o_irq => irq_map(CORE_INT_EOF_LEVEL)(CORE_INT_EOF_VECTOR),
i_ilevel => conv_std_logic_vector(CORE_INT_EOF_LEVEL, 2),
i_ivector => conv_std_logic_vector(CORE_INT_EOF_VECTOR, 4),
i_io => t_int_eof,
t_io => open,
o_io => open,
i_initdir => x"0000",
i_initoutval => x"0000"
);
--Interrupt for End of Frames:
t_int_eof<="00000000"&t_eofb(3) & t_eofa(3)&t_eofb(2) & t_eofa(2)& t_eofb(1) & t_eofa(1)& t_eofb(0) & t_eofa(0);
-- Map end of frames to interrupts.
Please give me an idea, because I don't know how to manage this sudden mistake..
Do you see anything wrong?
Why should not work the third call to ConfigurePin()?
Thanks in advance,
Michele
Replies (3)
RE: Call to tcDspFpgaGpio::ConfigurePin() makes the Dsp crash - Added by Michele Canepa almost 11 years ago
This is the crash dump on the serial output:
Unable to handle kernel NULL pointer dereference at virtual address 00000000
pgd = c5368000
[00000000] *pgd=c5312831, *pte=00000000, *ppte=00000000
Internal error: Oops: 80000005 [#1] PREEMPT
Modules linked in: nfsd exportfs fpga_i2c(O) fpga_gpio(O) fpga_ctrl(O) dsplinkk(O) cmemk(O) ipv6
CPU: 0 Tainted: G O (3.2.0 #1)
PC is at 0x0
LR is at fpga_gpio_IrqHandler+0x6c/0xac [fpga_gpio]
pc : [<00000000>] lr : [<bf09f344>] psr: 00000093
sp : c5847ea8 ip : 00000070 fp : c69e6080
r10: bf09f840 r9 : 00000004 r8 : 00000004
r7 : 00000002 r6 : c53f1500 r5 : 00000002 r4 : 00000000
r3 : 00000000 r2 : 0000000c r1 : c05e0434 r0 : 000000f7
Flags: nzcv IRQs off FIQs on Mode SVC_32 ISA ARM Segment user
Control: 0005317f Table: c5368000 DAC: 00000015
Process ARM_FD (pid: 2421, stack limit = 0xc5846270)
Stack: (0xc5847ea8 to 0xc5848000)
7ea0: 0000000c 00000070 00000000 00000000 00000000 c69e6002
7ec0: 00000001 00000001 c0642e84 c5153e00 00000001 bf0916b4 00000002 00000000
7ee0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
7f00: c5847f28 c40f3ee0 000000d1 c05df394 00000000 00000000 c064e190 c0054288
7f20: c05df394 c40f3ee0 c5847f50 c05df394 c40f3ee0 000000d2 0000ffff fee26088
7f40: 0000000d c064e190 00000000 c0054430 00000001 c05df394 c05dad24 c00562b8
7f60: 00001000 c0053c3c febfd000 c01657b4 c0165734 00000030 00000000 febfd000
7f80: 00000000 00000000 00000000 40052000 bef27c34 c0053c3c 000000f5 c0009c84
7fa0: 00031e48 0000981c 20000010 c000919c 00031e48 c018e034 00000001 00000001
7fc0: 00031e48 00000000 000092e8 00000000 00000000 00000000 40052000 bef27c34
7fe0: 00000000 bef27a70 00009814 0000981c 20000010 ffffffff 00000000 00000000
[<bf09f344>] (fpga_gpio_IrqHandler+0x6c/0xac [fpga_gpio]) from [<bf0916b4>] (fpga_ctrl_irq_router+0xac/0x164 [fpga_ctrl])
[<bf0916b4>] (fpga_ctrl_irq_router+0xac/0x164 [fpga_ctrl]) from [<c0054288>] (handle_irq_event_percpu+0x30/0x184)
[<c0054288>] (handle_irq_event_percpu+0x30/0x184) from [<c0054430>] (handle_irq_event+0x54/0x74)
[<c0054430>] (handle_irq_event+0x54/0x74) from [<c00562b8>] (handle_simple_irq+0x78/0xa4)
[<c00562b8>] (handle_simple_irq+0x78/0xa4) from [<c0053c3c>] (generic_handle_irq+0x30/0x44)
[<c0053c3c>] (generic_handle_irq+0x30/0x44) from [<c01657b4>] (gpio_irq_handler+0x80/0xac)
[<c01657b4>] (gpio_irq_handler+0x80/0xac) from [<c0053c3c>] (generic_handle_irq+0x30/0x44)
[<c0053c3c>] (generic_handle_irq+0x30/0x44) from [<c0009c84>] (handle_IRQ+0x60/0x84)
[<c0009c84>] (handle_IRQ+0x60/0x84) from [<c000919c>] (_irq_usr+0x3c/0x80)
Code: bad PC value
---[ end trace 77b8a47c35f36e4c ]---
Kernel panic - not syncing: Fatal exception in interrupt
[<c000d518>] (unwind_backtrace+0x0/0xe0) from [<c037cbe4>] (panic+0x58/0x188)
[<c037cbe4>] (panic+0x58/0x188) from [<c000c05c>] (die+0x1b8/0x1f8)
[<c000c05c>] (die+0x1b8/0x1f8) from [<c000e364>] (_do_kernel_fault+0x64/0x84)
[<c000e364>] (_do_kernel_fault+0x64/0x84) from [<c000e550>] (do_page_fault+0x1cc/0x1e0)
[<c000e550>] (do_page_fault+0x1cc/0x1e0) from [<c0008680>] (do_PrefetchAbort+0x34/0x98)
[<c0008680>] (do_PrefetchAbort+0x34/0x98) from [<c00090d8>] (_pabt_svc+0x38/0x80)
Exception stack(0xc5847e60 to 0xc5847ea8)
7e60: 000000f7 c05e0434 0000000c 00000000 00000000 00000002 c53f1500 00000002
7e80: 00000004 00000004 bf09f840 c69e6080 00000070 c5847ea8 bf09f344 00000000
7ea0: 00000093 ffffffff
[<c00090d8>] (_pabt_svc+0x38/0x80) from [<bf09f344>] (fpga_gpio_IrqHandler+0x6c/0xac [fpga_gpio])
[<bf09f344>] (fpga_gpio_IrqHandler+0x6c/0xac [fpga_gpio]) from [<bf0916b4>] (fpga_ctrl_irq_router+0xac/0x164 [fpga_ctrl])
[<bf0916b4>] (fpga_ctrl_irq_router+0xac/0x164 [fpga_ctrl]) from [<c0054288>] (handle_irq_event_percpu+0x30/0x184)
[<c0054288>] (handle_irq_event_percpu+0x30/0x184) from [<c0054430>] (handle_irq_event+0x54/0x74)
[<c0054430>] (handle_irq_event+0x54/0x74) from [<c00562b8>] (handle_simple_irq+0x78/0xa4)
[<c00562b8>] (handle_simple_irq+0x78/0xa4) from [<c0053c3c>] (generic_handle_irq+0x30/0x44)
[<c0053c3c>] (generic_handle_irq+0x30/0x44) from [<c01657b4>] (gpio_irq_handler+0x80/0xac)
[<c01657b4>] (gpio_irq_handler+0x80/0xac) from [<c0053c3c>] (generic_handle_irq+0x30/0x44)
[<c0053c3c>] (generic_handle_irq+0x30/0x44) from [<c0009c84>] (handle_IRQ+0x60/0x84)
[<c0009c84>] (handle_IRQ+0x60/0x84) from [<c000919c>] (_irq_usr+0x3c/0x80)
Thanks,
Michele
RE: Call to tcDspFpgaGpio::ConfigurePin() makes the Dsp crash - Added by Michael Williamson almost 11 years ago
Hi Michele,
Set the CORE_INT_EOF_LEVEL to 1.
Our framework uses 2 levels (2 seperate GPIO interrupt lines between FPGA and OMAP-L138). By default, level 0 is used for cores managed by the ARM and level 1 is used for cores managed by the DSP.
The FPGA is asserting an interrupt condition on Level 0, and the ARM is catching the interrupt and doesn't have a registered handler for the vector being reported (because the DSP is supposed to be handling it).
You should also use level 1 on set_hw_interrupt_level().
If you need both levels on the DSP, then you will need to modify the ARM linux driver core to not attempt to service level 0 interrupts from the FPGA.
-Mike
RE: Call to tcDspFpgaGpio::ConfigurePin() makes the Dsp crash - Added by Michele Canepa almost 11 years ago
Thanks Mike!
That was definitely the reason of the crash.
Thank you.
Michele
