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Memcpy data transfer error from FPGA address space to CMEM-allocated data buffers.
Added by Michele Canepa almost 11 years ago
Dear Sirs,
I have implemented a ping pong buffer to transfer via EMIF some data from a Block-RAM on FPGA to a shared memory between ARM and DSP allocated by CMEM.
RAM is filled with 16 bit samples coming from an ADC: I have "hacked" your EMIFA_interface vhdl module to provide, on CS4, a 10 bit addressing, in order to hook up to 16 Block-RAM with 1024 samples depth each, and make them visible to EMIF, starting from the address 0x64000000.
Data Transfer is triggered by a ping/pong signal routed to an FPGA interrupt on DSP side.
Now, when I try to perform a memcpy inside the interrupt routine, I find that all the samples are copied correctly, except the first sample, which is correct on FPGA but is copied wrong on the CMEM buffer.
After a short time the copy is successful, but I need to check the validity of the data with a do-while loop, and this operation slows down the transfer too much.
I thought it was a problem of cache, but I disabled all the cache with MAR registers and the problem persists.
I attach the following files:
-fpga_interface.cpp is the DSP interface to fpga.
-EMIFA_ifaceMC.vhd is the modified interface, with the customized cs4 address space.
-acq_eng_seq_top.vhd is the module in which the Block RAM are instanced.
Thank you very much in advance,
Regards,
Michele Canepa
| EMIFA_ifaceMC.vhd (6.28 KB) EMIFA_ifaceMC.vhd | |||
| acq_eng_seq_top.vhd (4.17 KB) acq_eng_seq_top.vhd | |||
| fpga_interface.cpp (3 KB) fpga_interface.cpp |
Replies (3)
RE: Memcpy data transfer error from FPGA address space to CMEM-allocated data buffers. - Added by Michael Williamson almost 11 years ago
I think you should setup a chipscope in the FPGA and watch the EMIFA transactions and see if the data is being posted to the bus per the timing specs. I don't see anything obviously wrong in your ISR code. If you have to hit each register twice to get the proper value, then it sounds like the address isn't being held on the bus long enough for your read to complete a decode and present the data and you may need to extend the EMIFA read strobe or wait states. Accessing it twice in a row is likely keeping the address bus stable for the second read to be successful.
Have you configured the EMIFA wait states, etc. for CS4 to be consistent with your bus address / decode read logic? You will need to do that somewhere in your u_Boot and/or kernel code or your DSP application. I don't know if we modify the CS4 status from their defaults off the top of my head.
-Mike
RE: Memcpy data transfer error from FPGA address space to CMEM-allocated data buffers. - Added by Michele Canepa almost 11 years ago
Dear Mike,
When you say to configure the emif wait states etc., you mean modifying, for example, the file "u-boot-mitydspl138/board/davinci/mityomapl138/mityomapl138.c" ?
In that file I see these configurations:
code:
emif_regs->AB3CR = /* CE 4 address space config register /
(0 << 31) | / Select Strobe /
(0 << 30) | / Extended Wait /
(0x0 << 26) | / Write Setup-1 in EMA_CLK /
(0x0 << 20) | / Write strobe-1 in EMA_CLK /
(0x0 << 17) | / Write Hold-1 in EMA_CLK /
(0x0 << 13) | / Read Setup-1 in EMA_CLK /
(0x5 << 7) | / Read Strobe-1 in EMA_CLK /
(0x0 << 4) | / Read Hold-1 in EMA_CLK /
(0 << 2) | / Turn-Around in EMA_CLK /
(1); / Bus Width (16 bits data bus) */
emif_regs->AB4CR = /* CE 5 address space config register /
(0 << 31) | / Select Strobe /
(0 << 30) | / Extended Wait /
(0x0 << 26) | / Write Setup-1 in EMA_CLK /
(0x0 << 20) | / Write strobe-1 in EMA_CLK /
(0x0 << 17) | / Write Hold-1 in EMA_CLK /
(0x0 << 13) | / Read Setup-1 in EMA_CLK /
(0x5 << 7) | / Read Strobe-1 in EMA_CLK /
(0x0 << 4) | / Read Hold-1 in EMA_CLK /
(0 << 2) | / Turn-Around in EMA_CLK /
(1); / Bus Width (16 bits data bus) */
end code.
Seems that CE4 is configured with the same timings as CE5. Do you agree?
Another question: in my acqusition control core module, I synchronize data out signal with clock when reading.
code:
reg_read: process(ema_clk)
begin
if rising_edge(ema_clk) then
if i_cs = '1' then
o_datab <= t_dataout;
else
o_datab <= (others=>'0');
end if;
end if;
end process;
end code
I inserted this process because I've read a similar thing in your reg_read process, for example, in gpio.vhd source.
Is it correct? Can this be the issue? Have I got any alternative instead doing so?
Anyway I try to debug it with Chipscope, but I need a while to configure it.
Thank you for your attention,
Regards,
Michele
RE: Memcpy data transfer error from FPGA address space to CMEM-allocated data buffers. - Added by Michele Canepa almost 11 years ago
Hello Mike,
I've solved the problem! Actually it was a timing problem related to the access policy to the emif.
I eliminated the one-clock-delay due to the output flip-flop (reg_read), substituting it with a multiplexer.
Now it works smoothly: thank you for highlighting a possible timing issue!!
Best Regards,
Michele Canepa
