Mity CPU Platforms » MityDSP-L138 (ARM9 Based Platforms)

Hi Martin,

I have never personally used the uPP in this setup, however, it looks like it should be possible.

For hardware details please refer to http://www.criticallink.com/wp-content/uploads/2014/01/MityDSP-L138-Carrier-Board-Design-Guide.pdf for details on how the pins are routed to the edge connector. Note that the names for some of these pins do not inform of all their possible configurations (i.e. the pin listed as LCD_D [1] can be configured to be UPP_XD [9]). Therefore, please also utilize Table 3-27 in http://www.ti.com/lit/ds/symlink/omap-l138.pdf for a list of all the possible uPP pins and their alternate names.

For software details please refer to Chapter 33 of http://www.ti.com/lit/ug/spruh77c/spruh77c.pdf. Note that Table 33-4 specifically calls out a 2-Channel Receive mode. Also, the tcDspUpp class in our MDK should offer software support you can leverage, if you are planning on receiving data from the uPP in the DSP.

Thanks,
\Greg

Hello Greg,
many thanks for your answer.
as i Know LCD[x] pins are outputs. and on the MityDsp is see U9 which is a SN54LVC157A multiplexer.
We also see some 2k Resistors to GND in these lines. (R54-R62).
Thats why I ask if these Signals are directly routed to the DSP.

Regards Martin

Hi Martin,

LCD [8] - LCD [15] also function as Boot Mode Selection pins. The SN54LVC157A is used to change the pull-up/pull-down configuration to allow for different boot modes.

Once the system is booted these pins can be reconfigured in software (via internal pin muxing) to act as inputs UPP_XD [0] - UPP_XD [7]. These pins are direct connections between the ARM/DSP and edge connector. The boot mode settings will act as a mixture of pull-ups and pull-downs on the these lines, but they should not have an affect on the received data.

Thanks,
\Greg

Hello Greg,
many thanks for your answers.
I will try that configuration, takes a while.

Great Support Many Thanks again.
Regards
Martin