Creating FPGA Base-Project - core manager problem
Added by Christian Rückl about 9 years ago
I've started with the FPGA-design in ISE Webpack 14.4.
I added all files from "MDK_2012-08-10\fpga\vhdl" to the project and also the "EMIFA_dcm.xco" file. I tried to regenerate this core in my project but I don't know why, but it won't work.
When I open the core manager all cores are grayed out and in the console i get these errormessages:
ERROR:sim:569 - Failed to set default project options.
ERROR:sim:621 - Unable to create project from file 'C:\HS\Master\FPGA_Software\ADPSEC_V1\ipcore_dir\coregen.cgp'.
ERROR:encore:273 - Unable to migrate C:\HS\Master\FPGA_Software\ADPSEC_V1\ipcore_dir\coregen.cgp to C:\HS\Master\FPGA_Software\ADPSEC_V1\ipcore_dir\coregen.cgc
When I click on a core in the window right to the IP catalog there is written:
"You may browse the IP Catalog but you will not be able to generate any cores until you open or create a project."
Which project i have to open?
Or whats going there wrong?
Can it be a licensing problem? I haven't a license except for the ISE Webpack.
The ISE Webpack license should be sufficient for what you are trying to do.
Try opening one of the projects in MDK\examples\industrial_io\fpga\build_* and see what that tells you. You will most likely be asked to migrate those projects to the 14.4 tools, but after that everything should build for you. Hopefully you can use that as an example project for what you are doing.
Let us know if you have any problems.
RE: Creating FPGA Base-Project - core manager problem - Added by Christian Rückl about 9 years ago
i opend the "build_lcd_rev_c" example project and migrate it to the 14.4 version. I think the migrtion works but there are some files needed what i can't find in the MDK.
see the attached picture. Therfore i couldn't try to test it.
More or less i would need only a working example project which may include the SPI and the GPIO core
can it be, that the migration to the 14.4 ISE of the DCM_core isn't working?
Hopefully, you can give me input on this.
Do i have to enter some special settings in my ISE software.
We do not currently distribute the vhdl for the MDK cores that are missing from that project. We do, however, distribute the netlists, which will allow you to build that project. Include the netlists from MDK\fpga\cores\build_spartan6 and you should be able to get that project to build.
The DCM should have migrated to 14.4 properly. However, there really isn't too much to that DCM, so you can always try creating a "Clocking Wizard" Xilinx IP core in its place if you think that is what is causing you trouble.