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EMC Emissions from MityArm 335X MOdule

Added by Michael Schantzen over 8 years ago

Hi,

We have done a number of EMC frequency scans on our product using the MityArm 3352-GX-X27-RC module. There are a couple of frequencies that are out of specification to meet the IEC 61000-6-3 Emissions for Residential Environments. I would like to get a list of fundamental frequencies(crystal frequencys, DDR3 bus speed, etc.) used on the 3352-GX-X27-RC module. We are seeing some out of spec quasi-peak readings at frequencies of 192MHz, 210MHz and 292.96Mhz. I have not ruled out that these noise peaks are being generated from our base board but so far I cannot correlate these peaks with any base operating frequencies on our base board. Below is the complete table of frequency scans.

Trace Frequency Level Limit
(MHz) ( dBμV) ( dBμV) (dB)
1 QP 50.0 27.75 40.00 -12.25
1 QP 70.0 36.96 40.00 -3.04
1 QP 100.0 29.17 40.00 -10.83
1 QP 110.0 34.81 40.00 -5.19
1 QP 124.96 24.80 40.00 -15.20
1 QP 130.0 27.92 40.00 -12.08
1 QP 140.0 31.86 40.00 -8.14
1 QP 170.0 25.64 40.00 -14.36
1 QP 180.0 33.11 40.00 -6.89
1 QP 190.0 43.30 * 40.00 3.30
1 QP 200.0 36.23 40.00 -3.77
1 QP 210.0 42.38 * 40.00 2.38
1 QP 224.96 28.31 40.00 -11.69
1 QP 250.0 44.29 47.00 -2.71
1 QP 292.96 51.69 * 47.00 4.69

Thanks,
Mike


Replies (6)

RE: EMC Emissions from MityArm 335X MOdule - Added by Michael Williamson over 8 years ago

Hi Mike,

The module has 2 crystals on it, a 24 MHz (connected to ARM) and a 32 KHz (connected to PMIC).

I don't know off-hand what the switching supply freqencies are on the PMIC, but I would think they aren't above 2 MHz (probably a lot lower).

The arm uses a pretty sophisticated set of PLLs and clock tree to drive the various peripherals, DDR, and core CPU rate. The PLL rates change based on operating point, which by default with the current kernel is a 720 MHZ CPU.

Rather then try to figure out what all the clock outputs are by hand, you should be able to dump out the complete clock tree (all of the frequencies used by the various peripherals) by mounting the debug file system and looking at the clock tree. Check this page out for more information (about half way down), http://processors.wiki.ti.com/index.php/Clock_Framework_User_Guide.

I haven't tried this on the AM335x, but have used it on the DM8148. I am fairly certain the framework is there and enabled, but you may need to rebuild the kernel to enable it.

Something like this might list all the frequencies:

mkdir /mnt/debug
mount -t debugfs debugfs /mnt/debug
find /mnt/debug -name rate | xargs cat

If you are still having trouble let me know and I can set up a rig here and help walk you through dumping out the data.

-Mike

RE: EMC Emissions from MityArm 335X MOdule - Added by Michael Schantzen over 8 years ago

Hi Mike,

I had our lead software engineer try to dump the clock tree per the information you provided but he could not access it.
I would appreciate if you could set up a rig and help us through it.

Thanks,

Mike

RE: EMC Emissions from MityArm 335X MOdule - Added by Michael Williamson over 8 years ago

Hi Mike,

We needed to enable a kernel flag here. Here is a dump of the PLL derived clock tree from our dev kit. Most of these frequencies don't leave the CPU. The frequencies should be the same for you with the exception of perhaps a baud rate of a serial port, etc. To enable dumping the clocks, you need to rebuild the kernel with CONFIG_PM_DEBUG and CONFIG_DEBUG_FS enabled.

Hope this helps.

-Mike

clock-name                     parent-name                    rate       use-count
vtp_clk                        sys_clkin_ck                   12000000   0
timer7_ick                     l4ls_gclk                      100000000  1
timer6_ick                     l4ls_gclk                      100000000  1
timer5_ick                     l4ls_gclk                      100000000  1
timer4_ick                     l4ls_gclk                      100000000  1
timer3_ick                     l4ls_gclk                      100000000  1
timer2_ick                     l4ls_gclk                      100000000  1
timer1_ick                     l4_wkup_gclk                   100000000  1
timer0_ick                     l4_wkup_gclk                   100000000  1
clkout2_ck                     sysclkout_pre_ck               32768      0
sysclkout_pre_ck               clk_32768_ck                   32768      0
gfx_ick                        gfx_l3_gclk                    200000000  0
gfx_fclk                       gfx_fclk_clksel_ck             200000000  0
gfx_fclk_clksel_ck             sysclk1_ck                     200000000  0
mmc_clk                        per_192mhz_clk                 96000000   0
lcd_gclk                       disp_pll_clk                   300000000  1
gpio3_dbclk                    clk_32khz_ck                   32768      0
gpio2_dbclk                    clk_32khz_ck                   32768      0
gpio1_dbclk                    clk_32khz_ck                   32768      0
gpio0_dbclk                    gpio0_dbclk_mux_ck             32000      0
gpio0_dbclk_mux_ck             clk_rc32k_ck                   32000      0
cpsw_cpts_rft_clk              dpll_core_m5_ck                250000000  0
cpsw_5mhz_clk                  cpsw_50mhz_clk                 5000000    0
cpsw_50mhz_clk                 sysclk2_ck                     50000000   0
cpsw_125mhz_gclk               sysclk2_ck                     125000000  1
cpsw_250mhz_clk                sysclk2_ck                     250000000  0
sysclk_div_ck                  dpll_core_m4_ck                200000000  0
clk_24mhz                      per_192mhz_clk                 24000000   1
debug_clka_gclk                sysclk1_ck                     200000000  0
l4ls_gclk                      core_100mhz_ck                 100000000  27
l4fw_gclk                      core_100mhz_ck                 100000000  1
l3s_gclk                       core_100mhz_ck                 100000000  2
l4hs_gclk                      sysclk1_ck                     200000000  1
l4_wkup_gclk                   sysclk1_ck                     100000000  6
gfx_l3_gclk                    sysclk1_ck                     200000000  0
l3_gclk                        sysclk1_ck                     200000000  6
l4_rtc_gclk                    sysclk1_ck                     100000000  0
l4_wkup_aon_gclk               sysclk1_ck                     200000000  1
l3_aon_gclk                    sysclk1_ck                     200000000  1
wkup_m3_fck                    l4_wkup_aon_gclk               200000000  0
wdt1_fck                       clk_rc32k_ck                   32000      0
wdt1_ick                       l4_wkup_gclk                   100000000  0
wdt0_fck                       clk_rc32k_ck                   0          0
wdt0_ick                       l4_wkup_gclk                   100000000  0
usbotg_fck                     usb_pll_clk                    960000000  1
usbotg_ick                     l3s_gclk                       100000000  1
uart6_ick                      l4ls_gclk                      100000000  1
uart5_ick                      l4ls_gclk                      100000000  1
uart4_ick                      l4ls_gclk                      100000000  1
uart3_ick                      l4ls_gclk                      100000000  1
uart2_ick                      l4ls_gclk                      100000000  1
uart1_ick                      l4_wkup_gclk                   100000000  1
uart6_fck                      per_192mhz_clk                 48000000   1
uart5_fck                      per_192mhz_clk                 48000000   1
uart4_fck                      per_192mhz_clk                 48000000   1
uart3_fck                      per_192mhz_clk                 48000000   1
uart2_fck                      per_192mhz_clk                 48000000   1
uart1_fck                      per_192mhz_clk                 48000000   1
tptc2_ick                      l3_gclk                        200000000  1
tptc1_ick                      l3_gclk                        200000000  1
tptc0_ick                      l3_gclk                        200000000  1
tpcc_ick                       l3_gclk                        200000000  1
lcdc_ick                       sysclk1_ck                     200000000  0
timer7_fck                     sys_clkin_ck                   24000000   0
timer6_fck                     sys_clkin_ck                   24000000   1
timer5_fck                     sys_clkin_ck                   24000000   1
timer4_fck                     sys_clkin_ck                   24000000   0
timer3_fck                     sys_clkin_ck                   24000000   0
timer2_fck                     sys_clkin_ck                   24000000   1
timer1_fck                     sys_clkin_ck                   24000000   1
timer0_fck                     clk_rc32k_ck                   32000      0
spinlock_fck                   l4ls_gclk                      100000000  0
spi1_ick                       l4ls_gclk                      100000000  1
spi0_ick                       l4ls_gclk                      100000000  1
spi1_fck                       per_192mhz_clk                 48000000   0
spi0_fck                       per_192mhz_clk                 48000000   0
smartreflex1_ick               l4_wkup_gclk                   100000000  0
smartreflex1_fck               sys_clkin_ck                   24000000   0
smartreflex0_ick               l4_wkup_gclk                   100000000  0
smartreflex0_fck               sys_clkin_ck                   24000000   0
sha0_fck                       l3_gclk                        200000000  0
rtc_ick                        l4_rtc_gclk                    100000000  0
rtc_fck                        clk_32khz_ck                   32768      2
rng_fck                        l4ls_gclk                      100000000  0
pka_fck                        l4ls_gclk                      100000000  0
ocpwp_fck                      l4ls_gclk                      100000000  0
ocmcram_ick                    l3_gclk                        200000000  0
mmu_fck                        gfx_l3_gclk                    200000000  0
mmc2_fck                       mmc_clk                        96000000   0
mmc1_fck                       mmc_clk                        96000000   0
mmc0_fck                       mmc_clk                        96000000   0
mmc2_ick                       l4ls_gclk                      100000000  1
mmc1_ick                       l4ls_gclk                      100000000  1
mmc0_ick                       l4ls_gclk                      100000000  1
mlb_fck                        sysclk_div_ck                  200000000  0
mcasp1_fck                     sys_clkin_ck                   24000000   1
mcasp1_ick                     l3s_gclk                       100000000  0
mcasp0_fck                     sys_clkin_ck                   24000000   0
mcasp0_ick                     l3s_gclk                       100000000  0
mailbox0_fck                   l4ls_gclk                      100000000  0
lcdc_fck                       lcd_gclk                       300000000  4
l4ls_ick                       l4ls_gclk                      100000000  1
l4fw_ick                       core_100mhz_ck                 100000000  1
l4wkup_ick                     l4_wkup_aon_gclk               200000000  1
l4hs_ick                       l4hs_gclk                      200000000  1
ieee5000_fck                   l3s_gclk                       100000000  0
icss_iep_gclk                  l3_gclk                        200000000  0
icss_uart_gclk                 per_192mhz_clk                 192000000  0
icss_ocp_gclk                  l3_gclk                        200000000  0
i2c3_ick                       l4ls_gclk                      100000000  0
i2c3_fck                       per_192mhz_clk                 48000000   0
i2c2_ick                       l4ls_gclk                      100000000  0
i2c2_fck                       per_192mhz_clk                 48000000   0
i2c1_ick                       l4_wkup_gclk                   100000000  0
i2c1_fck                       per_192mhz_clk                 48000000   0
gpmc_fck                       l3s_gclk                       100000000  1
gpio3_ick                      l4ls_gclk                      100000000  1
gpio2_ick                      l4ls_gclk                      100000000  1
gpio1_ick                      l4ls_gclk                      100000000  1
gpio0_ick                      l4_wkup_gclk                   100000000  1
epwmss2_fck                    l4ls_gclk                      100000000  0
epwmss1_fck                    l4ls_gclk                      100000000  0
epwmss0_fck                    l4ls_gclk                      100000000  0
elm_fck                        l4ls_gclk                      100000000  1
debugss_ick                    l3_aon_gclk                    200000000  1
dcan1_ick                      l4ls_gclk                      100000000  0
dcan0_ick                      l4ls_gclk                      100000000  1
dcan1_fck                      sys_clkin_ck                   24000000   0
dcan0_fck                      sys_clkin_ck                   24000000   1
cpgmac0_ick                    cpsw_125mhz_gclk               125000000  2
control_fck                    l4_wkup_gclk                   100000000  1
clkdiv32k_ick                  clk_24mhz                      24000000   1
cefuse_iclk                    l4_cefsue_gclk                 100000000  0
cefuse_fck                     sys_clkin_ck                   24000000   0
l4_cefsue_gclk                 core_100mhz_ck                 100000000  0
aes0_fck                       l3_gclk                        200000000  0
adc_tsc_ick                    l4_wkup_gclk                   100000000  1
adc_tsc_fck                    sys_clkin_ck                   24000000   0
l3_instr_ick                   l3_gclk                        200000000  1
l3_ick                         l3_gclk                        200000000  1
core_100mhz_ck                 sysclk1_ck                     100000000  4
usb_pll_clk                    dpll_per_ck                    960000000  1
per_192mhz_clk                 dpll_per_m2_ck                 192000000  7
dpll_per_m2_ck                 dpll_per_ck                    192000000  1
dpll_per_ck                    sys_clkin_ck                   960000000  2
disp_pll_clk                   dpll_disp_m2_ck                300000000  1
dpll_disp_m2_ck                dpll_disp_ck                   300000000  1
dpll_disp_ck                   sys_clkin_ck                   300000000  1
emif_fw_fck                    l4fw_gclk                      100000000  1
emif_fck                       ddr_pll_clk                    151500000  1
ddr_pll_clk                    dpll_ddr_m2_ck                 303000000  1
dpll_ddr_m2_ck                 dpll_ddr_ck                    303000000  1
dpll_ddr_ck                    sys_clkin_ck                   303000000  1
mpu_fck                        dpll_mpu_m2_ck                 500000000  2
dpll_mpu_m2_ck                 dpll_mpu_ck                    500000000  1
dpll_mpu_ck                    sys_clkin_ck                   500000000  1
clk_32khz_timer                clk_32khz_ck                   32768      0
core_clk_out                   dpll_core_m4_ck                200000000  0
sysclk2_ck                     dpll_core_m5_ck                250000000  1
sysclk1_ck                     dpll_core_m4_ck                200000000  6
dpll_core_m6_ck                dpll_core_x2_ck                2000000000 0
dpll_core_m5_ck                dpll_core_x2_ck                250000000  1
dpll_core_m4_ck                dpll_core_x2_ck                200000000  1
dpll_core_x2_ck                dpll_core_ck                   2000000000 2
dpll_core_ck                   sys_clkin_ck                   1000000000 1
tclkin_ck                      none                           12000000   0
sys_clkin_ck                   virt_24m_ck                    24000000   11
virt_26m_ck                    none                           26000000   0
virt_25m_ck                    none                           25000000   0
virt_24m_ck                    none                           24000000   1
virt_19_2m_ck                  none                           19200000   0
clk_rc32k_ck                   none                           32000      0
clk_32khz_ck                   none                           32768      1
clk_32768_ck                   none                           32768      0

RE: EMC Emissions from MityArm 335X MOdule - Added by Michael Williamson over 8 years ago

Hi Mike,

Hold on on that last post. We were looking at the numbers and something does not look correct (there should not be a 2 GHz clock or a 1 GHz clock, and the CPU should be running at 700 MHz).

I may have posted this prematurely. Sorry.

-Mike

RE: EMC Emissions from MityArm 335X MOdule - Added by Michael Williamson over 8 years ago

Hi Mike,

OK, those numbers were for the CPU running at 500 MHz. The speed of the CPU may change based on what power management scheme (the CPU governor) that is selected in the kernel configuration.

Our default kernel selects "performance", which will ratchet the CPU frequency up and down based on CPU load. If you are using our kernel, the operating frequency may change based on how much load you put on the processor.

So, we will need to know a little more about your operation (or your software guy may need to get more involved) to nail down all of the PLL configuration settings in the CPU.

However, most of the peripheral clocks won't change, just the CPU clocks.

How can we help further, given this information?

-Mike

RE: EMC Emissions from MityArm 335X MOdule - Added by Michael Schantzen over 8 years ago

Hi Mike,

I am good for now. Thanks for the information.

Regards,

Mike

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