FPGA LVDS I/O standard termination

Added by Romain INGRASCIOTTA almost 8 years ago


I'm currently using the Mity-DSP pro and in my application the FPGA receive LVDS signals as inputs. The MityDSP pro is connected to an in-house extension board.

According to Mity-DSPpro datasheet, the MityDSPpro support 2.5V LVDS with 100 Ohm DCI termination. I just need a clarification on that. Does that mean that the split termination is already managed on the Board (reference pin (VRN) and (VRP) connected to separate 1% precision impedance-matching resistors for each FPGA bank) ? Or do we have to add some resistor to do the termination on our extension board (that's what we did for now with 100 ohm resistor between N and P wires of LVDS signals but if it already managed by the FPGA we would like to remove it) ?

Thanks in advance.



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