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Forum For FPGA developers

Subject Author Created Replies Last message
Programm FPGA via JTAG Dominique Lytwyn 12/03/2015 09:48 AM 2 Added by Dominique Lytwyn almost 6 years ago
RE: Programm FPGA via JTAG
Mity L138F FPGA -> OMAP interrupt lines Christopher Brunson 09/18/2014 08:32 AM 2 Added by Christopher Brunson about 7 years ago
RE: Mity L138F FPGA -> OMAP interrupt lines
FPGA LVDS I/O standard termination Romain INGRASCIOTTA 03/05/2014 10:13 AM 0
ASADSn / ASREn pin loc Leon Craven 12/12/2013 06:51 PM 1 Added by Michael Williamson almost 8 years ago
RE: ASADSn / ASREn pin loc
Additional Address Lines EA[19 downto 10] pin loc Leon Craven 12/11/2013 11:08 PM 4 Added by Leon Craven almost 8 years ago
RE: Additional Address Lines EA[19 downto 10] pin loc
How to use the sdram for FPGA and EMIFA bus in MityDSP-Pro board? 锋 曲 07/03/2013 02:13 AM 1 Added by Michael Williamson over 8 years ago
RE: How to use the sdram for FPGA and EMIFA bus in MityDS...
How does DSP configure FPGA program? 锋 曲 02/27/2013 08:21 PM 4 Added by 锋 曲 over 8 years ago
RE: How does DSP configure FPGA program?
About CE4 CE5 and INT6's pin asisgnment in FPGA Haibo Pang 02/04/2013 03:02 AM 1 Added by Michael Williamson almost 9 years ago
RE: About CE4 CE5 and INT6's pin asisgnment in FPGA
Mity-DSP Xilinx JTAG and Walking One Problem Julio Liriano 12/13/2012 04:56 PM 2 Added by Julio Liriano almost 9 years ago
RE: Mity-DSP Xilinx JTAG and Walking One Problem
JTAG adapter cable question Bob Clarke 04/25/2012 12:49 PM 1 Added by Michael Williamson over 9 years ago
RE: JTAG adapter cable question
MityDSP DSP/FPGA pinouts information request Peter Faill 04/06/2012 02:31 PM 1 Added by Michael Williamson over 9 years ago
RE: MityDSP DSP/FPGA pinouts information request
Looking for top-level module for FPGA Hands-on exercise for MDSP-Pro Bob Clarke 01/26/2012 12:48 PM 2 Added by Bob Clarke almost 10 years ago
RE: Looking for top-level module for FPGA Hands-on exerci...
MityDSP-Pro and host board schematics? Bob Clarke 01/17/2012 04:21 PM 3 Added by Bob Clarke almost 10 years ago
RE: MityDSP-Pro and host board schematics?
Bank switching for different FPGA applications Bob Clarke 01/11/2012 05:45 PM 4 Added by Bob Clarke almost 10 years ago
RE: Bank switching for different FPGA applications
MCS file settings Bob Clarke 01/12/2012 04:01 PM 1 Added by Michael Williamson almost 10 years ago
RE: MCS file settings
Pins used for MityDSP-Pro FPGA bootloader Bob Clarke 01/12/2012 11:29 AM 3 Added by Bob Clarke almost 10 years ago
RE: Pins used for MityDSP-Pro FPGA bootloader
Xilinx ISE project file for MityDSP-Pro Bob Clarke 01/11/2012 02:25 PM 2 Added by Bob Clarke almost 10 years ago
RE: Xilinx ISE project file for MityDSP-Pro
CE2, CE4, and CE5 addresses Bill Dickson 01/11/2012 04:09 PM 1 Added by Michael Williamson almost 10 years ago
RE: CE2, CE4, and CE5 addresses
Using FPGA cores and library Bill Dickson 01/11/2012 03:01 PM 1 Added by Michael Williamson almost 10 years ago
RE: Using FPGA cores and library
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