About CE4 CE5 and INT6's pin asisgnment in FPGA
Added by Haibo Pang almost 9 years ago
I want to design a sync fifo in the FPGA, which will use a synchronous interface in EMIF. So it is better
to use a separate CE pin other than CE2.
According to the MityDspProSpec.pdf, DSP pins CE2 CE4 CE5 INT4 INT5 INT6 are connected to the FPGA.
From the MityDsp-pro.ucf we knew that CE2 INT4 and INT5 are connected. But for CE4 CE5 and INT6,
are they connected? If They are,wich FPGA pins are they connected to?
RE: About CE4 CE5 and INT6's pin asisgnment in FPGA - Added by Michael Williamson almost 9 years ago
CE4 is connected to W15 of the FPGA (Bank 4).
CE5 is connected to AA15 of the FPGA (Bank 4).
GP  is connected to the FPGA_INIT_B signal on the FPGA, AC14. There is also an external 1K pullup to 3.3V on this net.
GP  is connected to the FPGA_DONE signal on the FPGA, AC24. There is also a 1K pullup and a 1K/diode net connected to this net.