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Bank switching for different FPGA applications

Added by Bob Clarke about 10 years ago

The MityDSP-Pro datasheet states the following:
----"Upon reset the Bank Control Logic defaults to bank zero for bootloading support.
----Following bootloading, the bank control logic is controlled by the FPGA. Refer to
----the MityDSP User’s Guide for more information on bank control logic."

Where can I locate the MityDSP User's Guide with this information?
Thanks.
-Bob Clarke


Replies (4)

RE: Bank switching for different FPGA applications - Added by Michael Williamson about 10 years ago

I don't know if Tom got you the Developer's Guides or not, but the bank control logic is generated out of the base_module.vhd (which you have the source code for). It basically updates an external serial shift register with the upper address lines for the parallel NOR PROM onboard. The EMIFA only provides a limited number of address lines, and more are required to fully address the PROM.

The bank selection logic is managed by the tcDspBankSelect class which is passed to the tcDspFlash class in our core library. If you hook up the lines called out in the bootloader image the same way as your final project, the FLASH control should "just work".

-Mike

RE: Bank switching for different FPGA applications - Added by Bob Clarke about 10 years ago

Mike,
thanks for the info. I understand that you folks have generated a number of cores that should automatically take care of this and other features of the FPGA. Our application is extremely simple and it will be most expedient for me to just whip something up from scratch rather than learning your system. Is it possible to just get a pin list with pin descriptions (or a complete UCF) for the FPGA? (I mentioned this in my last email to Tom also). That would answer 99% of my questions. (I've figured out most of what I need except for the bank switching and whether there is a reset coming into the FPGA.)
Thanks.
-Bob Clarke

RE: Bank switching for different FPGA applications - Added by Michael Williamson about 10 years ago

Hi Bob,

The only problem with "whipping stuff up from scratch" will be the fact that the bootloader application provided needs to be able to control the bank-switching serial shift register (via the FPGA) per the addressing scheme defined in order to access any DSP Code or FPGA Code stored above 4 MBytes of FLASH address space. As long as you put the DSP application code in the lowest 4 MB of FLASH, then you may be OK but the bootloader will attempt to post reads/writes to the FPGA during the boot phase.

The upper address bits of the PROM are controlled by a serial shift register (a separate 74 series IC on the board). The DSP reset line is hooked to the reset of the serial shift register in order to ensure the bottom bank of the PROM is selected on reset. The shift clock and data lines are connected to the FPGA via the base_module, which you can see in the UCF and vhdl files for the bootloader FPGA.

The UCF for the Bootlaoder image pretty much defines all of the FPGA to local module / DSP / PROM connections -- with the exception of the local DDRAM connected to the FPGA (are you using this RAM?). You should be able to determine the FPGA connections to the edge connector from the tables in MityDSP-PRO datasheet, but when I get a second I can create a full UCF file that calls out all of the connections on the device.

Sorry for the delay.

-Mike

RE: Bank switching for different FPGA applications - Added by Bob Clarke about 10 years ago

Mike,
my plan was to whip up the application but leave the boot loaders in place for both the DSP and FPGA. I assume that this will be ok if I put my application in the first application storage location. I only plan on using a single application. I just want to make sure that those lines default to nominal states in my application so that I don't switch banks.
Thanks.
-Bob

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