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CE2, CE4, and CE5 addresses

Added by Bill Dickson about 10 years ago

On the 1.2 GHz C6455 version of the MityDSP-Pro using the XC3S4000, what CE2, CE4, and CE5 EMIF address ranges are already used by the DSP/FPGA cores? What future-proof range of addresses do you recommend for "user" code to avoid conflict with the core addresses?

Thanks, Bill


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RE: CE2, CE4, and CE5 addresses - Added by Michael Williamson about 10 years ago

The FPGA cores stack up on the CE2 address space (0xA0000000). CE3 is reserved for the FLASH memory. CE4 is reserved for customer use (or use that requires different wait states, etc.).

On CE2, each core is designed to use 0x80 [bytes] of address space. You need a minimum of 2 cores installed to use our framework: the base_module at offset 0x0000 (or at base address 0xA0000000) and a console UART at offset 0x0080 (or base address 0xA0000080), so the total consumed range can be as small as 0xA0000000-0xA00000FF. By default, the CE4 space and upper address regions of the CE2 space are not used. If you want to stack up more of CL's "cores", you can pile them into the CE2 space.

Normally, we recommend that developers create a "custom core" using the vhdl\gpio.vhd (the GPIO module) as a template for the register access, then plug it into our framework. However, some customers prefer a wider memory access (for shared memory style interfaces, etc.) or need different wait-states then what is configured for CE2 and develop code to interface on the CE4 line. Because all the interfaces share the EMIFA Address and data lines, there is some logic in the C45x_EMIF interface module that combines logic for CE2 and CE4 together. You may need to modify it to meet your wait-state and timing closure requirements if you are spinning your own IP and want it to hang off of CE4. The EMIFA clock rate is configured to run at 100 MHz by default.

I'll try to post some more details on the EMIF interface in the next day or two. Sorry for the delay.

-Mike

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