Mity-DSP Xilinx JTAG and Walking One Problem

Added by Julio Liriano about 9 years ago

I've developed a JTAG test for our mothercard that the Mity DSP plugs into. I use the Xilinx JTAG to the FPGA on the Mity-DSP to walk a
one pattern on a 32-bit data bus to an Altera FPGA on the Mity-DSPs host card. All works smoothly until I get to bit 11 or IO B16 on the Xilinx FPGA.

When my walking one pattern reaches B16, the entire bus goes to all '1's and it seems as if the Xilinx FGPA has been knocked out of JTAG mode. The Altera
FPGA remains in JTAG mode and observes all the pins of the bus going high. If I avoid setting B16 to '1', this doesn't occur and the walking-one pattern
finishes successfully.

As I understand it, all general purpose Xilinx I/O to the connector are direct connections to the FPGA and nothing else. Is it possible that the TI dsp is
resetting the FPGA out of JTAG mode? I've tried running this test while the master reset was active and got the same result. Also, I dont understand why
that particular pin (B16) would cause a reset.

Replies (2)

RE: Mity-DSP Xilinx JTAG and Walking One Problem - Added by Michael Williamson about 9 years ago

All ones sounds like the FPGA got it's program pin pulled (it was reset). Is it possible you are driving P8 to Low? Or any other pins in your walking pattern? On the MityDSP, driving P8 of the FPGA low will reset the on-board 6711 processor. The first stage bootloader would then then reset the FPGA by driving the PROGRAM PIN. Your JTAG test should force all other pins on the part to input or High-Z with internal pullup resistors enabled. This is the unconfigured state of the FPGA for that particular module.

Can you confirm you are using a MityDSP-6711? (just want to make sure we are talking about the same part)

B16 only connects to the edge connector on the SOM, so I don't know why it would affect things unless your Host I/O card is doing something funny with that pin beyond routing it to your Altera Part.


RE: Mity-DSP Xilinx JTAG and Walking One Problem - Added by Julio Liriano about 9 years ago

I am using the base model MityDSP-6711 with the XC3S400 FPGA.

By default, I tri-state/make inputs any I/O pins not involved in the current test. The behavior you describe with pulling low
the P8 pin sounds very much like what is happening when I attempt to make B16 high. I will investigate this and make sure that
P8 is not being pulled low by mistake.

Once the B16 FPGA signal is on our host card, it goes directly to our Altera FGPA. Other than a pull-up resistor, there is nothing
else hanging off that line.

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