JTAG Interface
Added by Thomas Catalino about 1 month ago
(Posted on behalf of a customer)
On my existing system, the Max10 FPGA has the USB Blaster interface that uses 2.5V JTAG levels that I also route to a CPLD on my board. From the MitySOM-C10G documentation, the 10G uses 1.8V JTAG Levels.
- Do you know if my Max10 2.5V Levels will be compatible with your 10G 1.8V Levels?
- Does the V_JTAG (1.8V) get generated on your MitySOM-C10G??? It does not appear to get generated on the Dev Board.
Replies (1)
RE: JTAG Interface - Added by Gregory Gluszek about 1 month ago
Hello,
Regarding the first question, unfortunately, the 2.5 V levels being used for the Max10 FPGA will not be compatible with MitySOM-C10G. The Intel® Cyclone® 10 GX Device Family Pin Connection Guidelines states that for JTAG pins TCLK, TMS, TDI "Do not drive voltage higher than 1.8-, 1.5-, or 1.2-V VCCPGM supply for the TCK pin. The TCK input pin is powered by the VCCPGM supply."
Regarding the second question, VCCPGM (1.8 V) is generated on the MitySOM-C10G.
Thanks,
Greg
