25.3 projects can't get recompiled
Added by Eleonora Haralanova 3 days ago
Hello,
I'm trying to recompile any of the design for 25.3 and even after installing the patch for Quartus Pro, I get errors and was not successful. For the Emif project, during analysis and synthesis I get the following:
Error(16827): Verilog HDL error at hps_emif_0_emif_io96b_hps_410_om5ocfq_emif_0_lpddr4_emif_io96b_cal_230_f7tihzy.sv(17): cannot open include file cal_io96b_interface.svh
Error(13363): Verilog HDL error at hps_emif_0_emif_io96b_hps_410_om5ocfq_emif_0_lpddr4_emif_io96b_cal_230_f7tihzy.sv(532): module "hps_emif_0_emif_io96b_hps_410_om5ocfq_emif_0_lpddr4_emif_io96b_cal_230_f7tihzy" ignored due to previous errors
Error(13785): VHDL Use Clause error at hps_emif_0_emif_io96b_hps_410_om5ocfq_emif_0_lpddr4_emif_io96b_lpddr4_emif_io96b_cal_410_dzz5cvq.vhd(190): design library "emif_io96b_cal_230" does not contain primary unit "hps_emif_0_emif_io96b_hps_410_om5ocfq_emif_0_lpddr4_emif_io96b_cal_230_f7tihzy"
Error(13827): Ignored construct rtl at hps_emif_0_emif_io96b_hps_410_om5ocfq_emif_0_lpddr4_emif_io96b_lpddr4_emif_io96b_cal_410_dzz5cvq.vhd(301) due to previous errors
Error(16827): Verilog HDL error at hps_emif_0_emif_io96b_hps_410_om5ocfq_emif_0_lpddr4_emif_io96b_lpddr4_410_fppumcy_arch_top.sv(17): cannot open include file emif_io96b_interface.svh
Error(13363): Verilog HDL error at hps_emif_0_emif_io96b_hps_410_om5ocfq_emif_0_lpddr4_emif_io96b_lpddr4_410_fppumcy_arch_top.sv(2678): module "hps_emif_0_emif_io96b_hps_410_om5ocfq_emif_0_lpddr4_emif_io96b_lpddr4_410_fppumcy_arch_top" ignored due to previous errors
I also have the few questions.
1. Are you using any IP that requires special license? I might be missing those.
2. Is the example design meant to be loaded and run on the SBC or is it just as an example of connections. I'm asking because the s0_axi4_mm_bridge of the FPGA_EMIF is not connected, which I interpret as the FPGA_EMIF not being used in this example, but maybe I'm wrong.
3. I don't have any experience with Agilex and the DDR control looks very different from the Arria 10 DDR4 control (which I have been using for the last 9 years). I'm used to having the FPGA user side being much wider (using MSGDMA i had 256-bit data bus going to/from the DDR4 controller, several MSGDMAs), but I don't see that in the example design. How do you achieve the high speeds?
4. I might need help connecting the design to the controller, can I post more specific questions about that here?
Thank you,
Eleonora Haralanova
Replies (4)
RE: 25.3 projects can't get recompiled - Added by Mike Fiorenza 3 days ago
Hi Eleonora,
Are you using Quartus Pro 25.3 version exactly? If so, do you also happen to be on Windows and this reference design project checked out in a long directory path? Looking online this may be a common Windows problem where if the file paths get too long they break in Windows. You could try moving the reference project to the C:\ drive directly and see if this issue goes away.
1. I don't think your error is a licensing problem. Those are usually more straight forward and tell you specifically it is a license issue.
2. Both. The EMIF example is in place as a starting point though, like you're stating that the EMIF is instantiated but nothing is hooked up to it. To give you something quick to start from so you could add logic to the design and hook it up to the EMIF to leverage the DDR memory space. So yes you're correct, the EMIF IP will calibrate the DDR when the system is taken out of reset but nothing will actually perform reads/writes to the DDR in this example, that is for the end user to add.
3. The EMIF IP is different as it is for the Agilex 5, however, in principle works very similar. There is a 256-bit wide AXI bus that is being exported from the IP. However, I think you're pointing out that I accidentally only set the pipeline bridge to be 32-bits wide. That is a miss on my part and can be increased to 256-bit wide to match the AXI width of the IP. I will correct this and increase it to 256 for future releases. So if you increase the s0_axi4_mm_bridge_0 to be 256-bit wide, then you'll have the full width you are expecting at the top-level. Lastly, I am only clocking the s0_axi4_clock_bridge for that subsystem with the hps_user0_clk which is only 100 MHz in the example. You could instead add an IOPLL to spin that to 200 MHz to get the full-bandwidth of the DDR clocked at 800 MHz. The DDR is 32-bit wide clocked at 800 MHz (DDR x2 is 1600 MHz) so effectively 32 bits x 1600 MHz is 51,200 Mbps / 256-bit AXI width is 200 MHz to clock the AXI to achieve full bandwidth.
4. Absolutely. Reach out with any questions you have.
RE: 25.3 projects can't get recompiled - Added by Eleonora Haralanova 3 days ago
Thank you, Mike, for your reply.
The problem really was the Windows inability to works with long paths. I was able to build all 3 projects.
About adding a IOPLL as a reference clock for the DDR controller - what are the actual clocks coming to the FPGA on clock pins? In the SDC I only saw 100 MHz (HPS_CLKIN_P) and 25 MHz (HPS_CLK_25MHz). The FPGA_CLKIN_P is not specified, but the fpga_emif_sybsys spesifies the ref clock is 100 MHz. Are there any other clocks available?
Eleonora
RE: 25.3 projects can't get recompiled - Added by Mike Fiorenza 3 days ago
Eleonora,
Glad to hear you were able to build the projects!
HPS_CLK_25MHz is a 25 MHz oscillator for the HPS (Clocks the ARM, peripheral clocks, etc) also is where the hps_user0_clk comes from
The rest of the clocks come from two programmable PLLs that are on the base board. These clocks can be seen in the link below:
https://support.criticallink.com/redmine/projects/mitysbc_a5/wiki/Customizing_the_On_Board_Silicon_Labs_PLLs
- Mike
RE: 25.3 projects can't get recompiled - Added by Mike Fiorenza 3 days ago
Eleonora,
If you are asking what clock to drive your IOPLL clock with, you should be able to use the same clock FPGA_CLKIN_P.
So FPGA_CLKIN_P would go to the EMIF IP for its internal PLL that gets spun up to clock the DDR interface and then you could also send it to your IOPLL to go from 100 to 200 MHz to clock the AXI interface.
- Mike
