Mity CPU Platforms » MityDSP (TI TMS320C6xxx Based Products)

(posted on behalf of a customer who is using the MityDSP-Pro)

I've been trying to put an interrupt service routine (ISR) and the data it touches into L1P & L1D on the c6455 (MityDSP-Pro). Using L2 for code & data works fine, but I can't get things to work if I put the ISR code in L1P. I have been loading & running via CCS (a related bootloader question at the end of this email).

I've tried a very simple ISR put in L2 with one L1D variable getting incremented, and that works fine. If I then try to put the ISR into L1P, the ISR doesn't get called. When I try to pause the DSP to look variables in CCS, this error window pops up:

Trouble Halting Target CPU:
Error 0x00000024/-1060
Error during: Register, Execution, 
An unknown error prevented the emulator from accessing the processor
in a timely fashion.
It is recommended to RESET EMULATOR.  This will disconnect each 
target from the emulator.  The targets should then be power cycled
or hard reset followed by an emureset and reconnect to each target.

I am using DSP/BIOS 5.41 and I'm using the ISR Dispatcher in the HWI ISR manager. Under Scheduling->HWI in the DSP/BIOS config tool, I am using a "RESET vector address" of 0x00800000 (the start of L2). Would that need to change to an L1 address? As I recall, your examples use L2. Do you have any examples using L1 or other suggestions?

I can provide more details of how I have things set up, but I thought I'd pass the general issue by you in case you are aware of some limitations on what I'm trying to do.

I am presently looking into L1 memory protection settings, since tests are showing the program stopping when I try to call a function I put in L1P. Maybe the bootstrapper/loader disables L1P (or leaves it disabled) and my DSP code needs to turn it back on? If that rings a bell, please let me know.