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From 06/09/2019 to 07/08/2019

07/08/2019

02:57 PM FPGA Development: Reference Project AnalogExpansionSuite query
Hi,
I have a custom board with
-- MityDspl-138F module (with FPGA)
-- No Ethernet port
-- UART,USB,SD CARD int...
Vivek Ponnani
10:05 AM Software Development: RE: uPP receive clock lower limitation in SDR (Single Data Rate mode)
Thanks Greg for your reply and sorry for the late reply.
I will forward your response to our FPGA team. They are u...
Vivek Ponnani

06/24/2019

04:38 PM Software Development: RE: uPP receive clock lower limitation in SDR (Single Data Rate mode)
Hi Vivek,
I believe the datasheet is saying that regardless of whether the clock is being used as DDR or SDR the ...
Gregory Gluszek

06/21/2019

08:05 AM Software Development: uPP receive clock lower limitation in SDR (Single Data Rate mode)
Hi,
I have a custom board with
-- MityDspl-138F module (with FPGA)
-- No Ethernet port
-- UART,USB,SD CARD int...
Vivek Ponnani
 

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