Activity
From 06/05/2024 to 07/04/2024
07/03/2024
- 02:19 PM Software Development: RE: MityDSP-L138 Power Draw in Deep Sleep? Waking ARM core from DSP core? Power and Sleep Controller (PSC)
- Michael Bisbano wrote in message#6697:
> Hi Jonathan,
> Thank you for the response, please let me know what you fi...
07/01/2024
- 09:16 PM Software Development: RE: MityDSP-L138 Power Draw in Deep Sleep? Waking ARM core from DSP core? Power and Sleep Controller (PSC)
- Hi Jonathan,
Thank you for the response, please let me know what you find out! The system as a whole must be under ... - 07:05 PM Software Development: RE: MityDSP-L138 Power Draw in Deep Sleep? Waking ARM core from DSP core? Power and Sleep Controller (PSC)
- Michael Bisbano wrote:
> Hi all,
>
> I was wondering if anyone had data on power draw for the MityDSP-L138 in dee... - Hi all,
I was wondering if anyone had data on power draw for the MityDSP-L138 in deep sleep? My application is bat... - 03:49 PM Software Development: RE: Serial port 2 issue, RS485, RTS drops to early
- Fred Weiser wrote in message#6688:
> Changing the timer is probably not in my best interest; my project supports dow...
06/27/2024
- 09:06 PM Software Development: RE: Serial port 2 issue, RS485, RTS drops to early
- Changing the timer is probably not in my best interest; my project supports down to 1200 baud with packets up to 256 ...
- 06:12 PM Software Development: RE: Serial port 2 issue, RS485, RTS drops to early
- Here's the snip:...
- 05:45 PM Software Development: RE: Serial port 2 issue, RS485, RTS drops to early
- Looks like wait_for_xmitr has a 10ms timeout, this might explain why the TXEN is enabled for a constant time. At low...
- 04:19 PM Software Development: RE: Serial port 2 issue, RS485, RTS drops to early
- What does your pinmux look like for UART2?
- 03:36 PM Software Development: RE: Serial port 2 issue, RS485, RTS drops to early
- Please see two attached scope traces; the second with a 7 character buffer, the first with a 16 character buffer. I w...
- 02:31 PM Software Development: RE: Serial port 2 issue, RS485, RTS drops to early
- It looks like (in the 3.2 kernel anyway) the only serial port driver that supports the delay_rts_after_send option is...
- 01:46 PM Software Development: RE: Serial port 2 issue, RS485, RTS drops to early
- Thanks for the ideas; I'm looking into the code cited above now; I don't have any new news there at this time.
Ho... - 01:05 PM Software Development: RE: Serial port 2 issue, RS485, RTS drops to early
- My suspicion is that the register read in wait_for_xmitr() is "lying" and the UART is actually still serializing the ...
- 08:47 PM Software Development: RE: RS485 Direction Control on UART1
- Seems like it could work. Good find.
- 07:17 PM Software Development: RE: RS485 Direction Control on UART1
- I did come across this application note from TI: https://www.ti.com/lit/ug/tidubw6/tidubw6.pdf?ts=1719509747706
(if ...
06/25/2024
- 09:59 PM Software Development: RE: Serial port 2 issue, RS485, RTS drops to early
- The kernel driver code for RS485 support can be found here: https://support.criticallink.com/gitweb/?p=linux-davinci....
- 06:58 PM Software Development: RE: Serial port 2 issue, RS485, RTS drops to early
- Seems a "paste" didn't work as expected...
SER_RS485_USE_GPIO is the same as 1<<5 - We are having a problem with serial port ttyS2 on our L138 SoM which I believe resides in the Linux driver or the TI ...
06/20/2024
- 07:57 PM Software Development: RE: RS485 Direction Control on UART1
- How long are you looking for?
The kernel documentation mentions getting extended distance for rs232 by using UTP c... - 03:43 PM Software Development: RE: RS485 Direction Control on UART1
- Hi Jonathan,
thanks for the quick response. I will look into the 8250 driver, it might be useful (if only for my ...
06/19/2024
- 07:09 PM Software Development: RE: RS485 Direction Control on UART1
- The serial 8250 driver has an rs485 mode which we extended to allow using a gpio to generate a RS485 TX enable. Howe...
- Hi all,
My application requires installation embedded in a battery power system with long wire. I would like acces...
06/10/2024
- 11:08 AM Software Development: RE: FPGA (FIFO) -> DSP (DMA) transfer problem
- There is a cross-bar that sits between EMIFA on the L138 and the DSP / ARM / peripheral masters.
When a read reque... - 07:52 AM Software Development: RE: FPGA (FIFO) -> DSP (DMA) transfer problem
- Thank you for answer.
We will conduct the above experiment later.
Currently, we are trying to increase the RD Clk...
06/05/2024
- 09:05 PM Software Development: RE: FPGA (FIFO) -> DSP (DMA) transfer problem
- Hello,
Based on the FPGA code you shared I believe that the primary issue you are having is that your FPGA code r... - 12:42 AM Software Development: RE: FPGA (FIFO) -> DSP (DMA) transfer problem
- Thank you for answer.
As you suggested, read Cache_and_Memory and
We proceeded by modifying the source as shown bel...
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