Activity
From 01/22/2014 to 02/20/2014
02/20/2014
- 02:39 PM FPGA Development: RE: HPS Memory Controller
- Nope, if you connect it to the HPS to FPGA bridge you can treat it more like a register that the code on the HPS read...
- 01:10 PM FPGA Development: RE: HPS Memory Controller
- Hi Dan,
Don't you mean connect it to the FPGA to HPS AXI bridge?
Our input data is processed in the FPGA.
Th... - 01:03 PM FPGA Development: RE: HPS Memory Controller
- At that rate it might be simpler to create a FIFO in the FPGA and connect it to the light weight HPS to FPGA bridge. ...
02/19/2014
- 05:33 PM FPGA Development: RE: HPS Memory Controller
- Also, I'm trying to by pass the SGDMA dispatcher and use the write master directly.
Jack - 05:32 PM FPGA Development: RE: HPS Memory Controller
- Hi Dan,
Our data is coming in at about 40 MHz,
Jack - 04:57 PM FPGA Development: RE: HPS Memory Controller
- Hi Jack,
Looking in the SGDMA dispatcher core user guide, it appears that if you use the extended descriptors you ... - 04:33 PM FPGA Development: RE: HPS Memory Controller
- Hi Dan,
Regarding the SGDMA Write Master Core. I looked through the document for this core and it doesn't give any... - 03:40 PM FPGA Development: RE: HPS Memory Controller
- Jack,
We do not currently have an example that uses a non-packetized Avalon stream. There should be an option in t... - 03:22 PM FPGA Development: RE: HPS Memory Controller
- Hi,
Do you have any write to HPS memory examples where I can send data into the memory in a continuous stream rath...
02/13/2014
- 03:02 PM FPGA Development: RE: Signal Tap & JTAG FPGA Programming
- Glad to hear you got it working.
Dan - 03:01 PM FPGA Development: RE: Signal Tap & JTAG FPGA Programming
- Hi Dan,
Yes it works with the rbf file and it works when I program it in Linux. No problems there.
I managed to... - 01:58 PM FPGA Development: RE: Signal Tap & JTAG FPGA Programming
- Hi Jack,
I've just created a wiki page for the steps that it takes to program the FPGA using the USB-Blaster, woul... - Hi,
I'm raised the issue before regarding programming the FPGA with JTAG.
I have tried programming via JTAG, th...
02/07/2014
- I am running into the current error while running bitbake:
jliriano@ArmDev:~/yocto/build$ bitbake u-boot
ERROR: ...
02/03/2014
- Posting on behalf of a customer:...
01/30/2014
- 10:01 AM FPGA Development: RE: Ethernet
- Edited my response. Good eye Dave. Thanks!
- 09:31 AM FPGA Development: RE: Ethernet
- Greg,
Only 2 "e"s in setenv, not three... Jack probably knows that, but just to be clear...
Dave
- 09:10 AM FPGA Development: RE: Ethernet
- Hi Jack,
Follow these steps to correct the ethernet:
1. Break into u-boot by resetting the system and hitting ...
01/29/2014
- 06:48 PM FPGA Development: RE: Ethernet Rev B
- Hi,
I just received your rev B module. We noticed that the ethernet doesn't work on this revision at all. Is there...
01/27/2014
- 12:56 PM FPGA Development: RE: Load FPGA Timeout Error
- Hi Jack,
I'm not sure what else to try other than trying to program the FPGA through a JTAG pod, which I believe y...
01/24/2014
- 01:57 PM FPGA Development: RE: Load FPGA Timeout Error
- Hi Dan,
I did what Adam suggested and it made no difference. I tried it without anything plugged in and still noth... - 01:21 PM FPGA Development: RE: Load FPGA Timeout Error
- Currently I do not believe that is the case, seeing as this problem is happening in both uboot and linux.
Have you... - 12:28 PM FPGA Development: RE: Load FPGA Timeout Error
- Could this be a OS issue that's causing it?
Can some one direct me the exact link where I can download the img fil...
01/22/2014
- 03:37 PM FPGA Development: RE: Load FPGA Timeout Error
- Your MSEL is currently 00000. Try changing S100-position3 to OFF to get an MSEL[4:0] of 00100. This will change the ...
- 03:11 PM FPGA Development: RE: Load FPGA Timeout Error
- Looking through the uboot source code it seems that the HPS is not able to set the FPGA into a reset mode. Which coul...
- 02:57 PM FPGA Development: RE: Load FPGA Timeout Error
- correct
- 02:56 PM FPGA Development: RE: Load FPGA Timeout Error
- Is the following the full error you received?...
- 02:34 PM FPGA Development: RE: Load FPGA Timeout Error
- Yes
- 02:33 PM FPGA Development: RE: Load FPGA Timeout Error
- was this from the **run fpgaload**?
- 02:31 PM FPGA Development: RE: Load FPGA Timeout Error
- Hi Dan,
I got an error: Failed with error code -1.
Jack - 02:29 PM FPGA Development: RE: Load FPGA Timeout Error
- Hi Jack,
This needs to be run during uboot, which you get to by pressing any key during the first 5 seconds of sta... - 02:13 PM FPGA Development: RE: Load FPGA Timeout Error
- Hi Dan,
The Linux OS on the board doesn't have run and saveenv. I tried to update it, but it doesn't have the apt-... - 01:33 PM FPGA Development: RE: Load FPGA Timeout Error
- ...
- 12:59 PM FPGA Development: RE: Load FPGA Timeout Error
- Hi Dan,
Regarding the uboot procedure, I have never worked with uboot before and the instructions on rocketboard i... - 12:33 PM FPGA Development: RE: Load FPGA Timeout Error
- Hi Adam,
I'm not sure what the default positions for the MSEL or which of the switches on board are for the MSEL. ... - 12:23 PM FPGA Development: RE: Load FPGA Timeout Error
- Hi Jack,
Please check the MSEL dip switches. These should be set to FPPx16 or FPPx32 for the FPGA Manager to be a... - 12:07 PM FPGA Development: RE: Load FPGA Timeout Error
- Hi Dan,
The same issue still occurs after power cycling.
I'm wondering if it's a hardware issue.
Jack - 10:43 AM FPGA Development: RE: Load FPGA Timeout Error
- Hi Jack,
We have not seen this issue yet. If you power cycle the board did this issue still occur?
Dan
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