Project

General

Profile

Activity

From 08/01/2024 to 08/30/2024

08/14/2024

01:48 AM MitySOM-C10GX Hardware Design: RE: JTAG Interface
Hello,
Regarding the first question, unfortunately, the 2.5 V levels being used for the Max10 FPGA will not be co...
Gregory Gluszek

08/09/2024

09:24 PM MitySOM-C10GX Hardware Design: JTAG Interface

(Posted on behalf of a customer)
On my existing system, the Max10 FPGA has the USB Blaster interface that uses 2...
Thomas Catalino

08/01/2024

12:52 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: MitySOM-5csx custom board PL fabric ethernet access
Hi,
Actually that timing issues were resolved and ping performance also well as of now without packet loss. And no...
Bhardwaj Kotha
 

Also available in: Atom

Go to top
Add picture from clipboard (Maximum size: 1 GB)