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FPGA Development

Forum for questions related to the FPGA fabric development of the MitySOM-A5E

Subject Author Created Replies Last message
PCIE_RP example design - IPs question Eleonora Haralanova 08/13/2026 01:41 PM 1 Added by Mike Fiorenza 6 days ago
RE: PCIE_RP example design - IPs question
HPS to FPGA Manager (Memory-Mapped) question Maxim Kanevsky 08/06/2026 04:56 PM 2 Added by Maxim Kanevsky 13 days ago
RE: HPS to FPGA Manager (Memory-Mapped) question
Custom Loopback based on mSG-DMA Example Design Maxim Kanevsky 07/28/2026 07:33 PM 4 Added by Mike Fiorenza 20 days ago
RE: Custom Loopback based on mSG-DMA Example Design
Not being able to Make jic Eleonora Haralanova 07/08/2026 07:08 PM 11 Added by Eleonora Haralanova about 1 month ago
RE: Not being able to Make jic
HPS/FPGA shared external memory Maxim Kanevsky 05/05/2026 04:28 PM 5 Added by Mike Fiorenza 3 months ago
RE: HPS/FPGA shared external memory
Signal Tap not working Maxim Kanevsky 05/11/2026 04:40 PM 2 Added by Maxim Kanevsky 3 months ago
RE: Signal Tap not working
Ethernet Interface for MitySOM-A5E Maxim Kanevsky 04/23/2026 06:14 PM 5 Added by Thomas Catalino 4 months ago
RE: Ethernet Interface for MitySOM-A5E
question regarding pin assignments for SFP example project Maxim Kanevsky 02/17/2026 07:53 PM 2 Added by Michael Williamson 6 months ago
RE: question regarding pin assignments for SFP example pr...
What is the recommended version of Quartus for MitySOM_A5? Maxim Kanevsky 08/27/2025 09:12 PM 6 Added by Thomas Catalino 12 months ago
RE: What is the recommended version of Quartus for MitySO...
Fail to program device Maxim Kanevsky 08/27/2025 09:07 PM 8 Added by Mike Fiorenza 12 months ago
RE: Fail to program device
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