Mity CPU Platforms » MityDSP-L138 (ARM9 Based Platforms)

In the hardware, the TPS65023 used for the MityDSP-L138 has the following voltages that are defaulted using the hardware strapping pins:

VDCDC1 -> 1.2 V (core)
VDCDC2 -> 1.8 V (mDDR, DVDD18, DVDD3318_C, FPGA bank voltages)
VDCDC3 -> 1.2 V (SATA_VDD, Spartan 6 VCCINT, PLL0 and PLL1 VDDA)
VLDO1 -> 1.8 V (not used)
VLDO2 -> 3.3 V (used for FPGA VCC AUX

The guys that wrote the driver for the tps65023 and submitted it to linux coded it based on some reference design for another board. They hardcoded the values for the board that had the tps65023 device on it and didn't bother completing the tps65023 driver by supporting all the possible voltage settings. TI seems to get away with this a lot with drivers they submit, claiming that they couldn't test the code for the other options (and so someone that has a board that needs those options has to submit patches to clean up the initial design). For example (as you pointed out), the VDCDC2 is hardcoded for 3.3V operation but the datasheet for the TPS65023 clearly states that the DCDC2 supports operation at both 1.8 V and 3.3V, and the MityDSP-L138 is using 1.8V operation. They don't even bother to check the status register to see if perhaps that scenario is happening. They just pound it to 3.3V.

This results in the sysfs voltage values being displayed incorrectly, and without a patch to the tps65023 driver to fix the tables and support proper initialization we cannot correct it.

At one point in time, we had tried to push a patch through to deal with this, but the TPS65023 was already being refactored as a lot of the PM plumbing was getting shuffled around and it was basically dropped (and it would no longer apply as the new drivers look anyway).

At the moment, we don't support enabling active power management for the MityDSP-L138. Though we DO support support adjusting the core voltage for varying the OPP -- the kernel code should take card of this when using the sysfs interface for OPP set_scaling. I don't believe the kernel will allow altering or disabling the voltage settings for anything but the core voltage. Though, I've never tried adjusting them via sysfs.

I am sorry for the inconvenience and the confusion.

-Mike

Mike, thank you for fast response.

In Linux 3.14 (from Yocto Project) this leads to disabling cpufreq because it cant locate CVDD regulator.

How you think can I simply change constraints? This doesn't broke my MityDSP?

Andrey, Can you share your linux 3.14 port. What did you have to change to get it working? Are you using device tree?

Thanks Jonathan

Jonathan, nothing special only setup kernel config (attached).
I use Yocto Project Daisy toolchain and kernel from git://git.yoctoproject.org/linux-yocto-3.14.git, branch "standard/base".

But I'm not checked all peripherals. Can confirm only console, ethernet and nand works. You can check my bootlog for more info.

On my own risk I change TPS65023 constraints and CPUFreq now works fine.

Andrey,

Not sure if its any help but I've pushed a work in progress 3.14 branch to our git. Its based off the mainline 3.14.y branch. Haven't been able to get SPI working so the ethernet isn't getting initialized as its configured from the config in the spi nor (you could hack the ethernet config to whichever config you need). Otherwise should have similar or hopefully more peripherals working. I used your tps patch, can't say for sure if its correct but it does work.

http://support.criticallink.com/gitweb/?p=linux-davinci.git;a=shortlog;h=refs/heads/mitydsp-linux-v3.14_wip

Jonathan, thank you, I will track your branch.