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uPP receive problem
Added by Scott Whitney over 12 years ago
Hello,
I am writing a linux uPP driver for bi-directional comms between the fpga and OMAP. From what I can tell the FPGA is receiving data from the OMAP correctly, but THe OMAP is not getting the return data from the FPGA. In our current configuration the FPGA needs to receive 3 16 bit words on channel A, and will respond with 3 16 bit words on channel B. Both messages are padded to 64 bytes to ensure DMA transfers. On the FPGA we have routed all the control signals to the J104 header of the IO board so we can capture Start, Wait, Enable and the clocks on both channels. I initiate a transfer and capture the start and enable on channel A, and 3 clocks later the start and enable on Channel B become active (this is what we expect). I never get an interrupt on the Channel B EOL or EOW. Can you help?
The driver has previously been tested in the digital loopback mode, so I feel the uPP was setup correctly and the transmit and receive memory buffers allocated correctly. I have also set the uPP receive channel (B) to ignore the start and enable signals. I still get no data. I assumed that as long as the uPP channel was getting a clock it would clock in whatever the state of the pins were. Any help would be appreciated, Scott
Replies (6)
RE: uPP receive problem - Added by Thomas Catalino over 12 years ago
Hi Scott -
Thanks for posting.
I talked to the guys about this problem that you're having. It sounds like any number of issues in the handshake between the FPGA and the uPP peripheral could be causing your issue. They mentioned Data Ready, Data Valid, etc, all needing to be dealt with / provided by the FPGA properly. In order to really assist they would probably need to dig into your design and roll up their sleeves with source code and timing diagrams, etc. If you'd like us to do that we can talk about setting up a vehicle to do that.
We've used this peripheral in numerous designs (5 to 10) running at speeds ranging from 27Mhz to the full 75Mhz speed with no issues, so we do not believe it to be a board design issue, but more than likely something in the handshake code in the FPGA.
I know this doesn't really help you at the moment. Feel free to give me a call if you'd like to talk it through further.
Thanks,
Tom
RE: uPP receive problem - Added by Scott Whitney over 12 years ago
Tom,
I understand the handshaking can be a problem. I have the uPP running with the highest divisor now at ~4.68 MHz xmit clock. My concern is that I have disabled the start and enable on the receive channel. With those disabled I believed that data will clock into the receive fifo as soon as the DMA descriptors are programmed. That is as long as there is a clock on that channels clock pin. We are using the clock on channel A, buffering it in the FPGA and using it as the tx clock from the FPGA. When I program the receive channel descriptors I see no data. It makes me think we are not driving the clock at the right level. The ucf file shows lvcmos18 for all the uPP pins. Is that the correct level, or should we be using lvcmos33? thanks, Scott
RE: uPP receive problem - Added by Michael Williamson over 12 years ago
On the MityDSP-L138F, the voltage domain for the UPP (and for the FPGA bank connected to the UPP) is 1.8 Volts.
I'm not entirely sure, on receive, you want to disable the start and enable lines. It might be useful to post your UPP register settings that you are configuring, as well as a scope or logic analyzer (or chipscope) traces of the data....
-Mike
RE: uPP receive problem - Added by Scott Whitney over 12 years ago
Mike,
I will attach the upp control settings and dma descriptor settings. I know in the end I want to use the enable on the receive channel. I had disabled that in testing just to see if any data was clocked in. What worries me is that with start and enable disabled in the control registers the receive channel should start clocking in data as soon as the descriptors are set, but I don't see anything.
| upp_reg.txt (4.74 KB) upp_reg.txt | register settings |
RE: uPP receive problem - Added by Michael Williamson over 12 years ago
Hi Scott,
Sorry for the delay. You are using the receive channel much differently than we typically do (we use the Start and Enable signals pretty much according to the diagrams shown in the UPP users guide, or now in the Technical Resource Manual for the OMAP-L138).
Looking though your code, I don't see where the EN bit of UPPCR (step 7 in the Initialization and Operation Procedure) is being set. Other than that, nothing is leaping out at me. Have you tried the TI E2E site? This is really an OMAP-L138 UPP specific question (not a MityDSP-L138 SOM issue), there might be more folks there that could point you to a solution.
-Mike
RE: uPP receive problem - Added by Scott Whitney over 12 years ago
Mike,
Thanks for looking at the snippets of code I sent you. I have set the enable bit in my driver. I didn't send the whole thing, its a hot mess right now. Yesterday I had our fpga designer switch the tx and rx channels between the fpga and omap. He did not attach any of the control lines to gpio on the J104 header for monitoring. I was then able to get bidirectional comms between the fpga and omap. I had him bring out the control lines again to gpio on the J104 header and the uPP did not receive data correctly. I have no idea why this would affect the uPP. Since I was only using those lines for debugging we will keep them disconnected and proceed. Thanks for your help, Scott
