"Quick steps to Build" may be inaccurate in Building fpga 231 webpage - MitySOM-5CSX Altera Cyclone V - Critical Link Support

BN"Quick steps to Build" may be inaccurate in Building fpga 231 webpage

The Building fpga 231 webpage (at https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/Building_fpga_231) seems to have incorrect steps

For example, the Linux steps say:
Launch the Intel Embedded Command Shell from /opt/intelFPGA/23.1/embedded/embedded_command_shell.sh

There is no EMBEDDED folder in 23.1, only for 20.1

Bob N

Replies (11)

MF RE: "Quick steps to Build" may be inaccurate in Building fpga 231 webpage - Added by Mike Fiorenza 3 days ago

Bob,

Thanks for catching that. I've updated the page to point to the correct command shell that is available.

/opt/intelFPGA/23.1/nios2eds/nios2_command_shell.sh

- Mike

BN RE: "Quick steps to Build" may be inaccurate in Building fpga 231 webpage - Added by Bob Nayar 2 days ago

Thanks, Mike.
Using this shell allows me to successfully do the "make generate_from_tcl"
HOWEVER,
when I do a "make all", I get this error:

<stuff deleted>
2026.09.18.12:56:25 Info: p0: *********************
2026.09.18.12:56:25 Info: p0:
2026.09.18.12:56:25 Info: p0: "fpga_ddr" instantiated altera_mem_if_ddr3_phy_core "p0"
2026.09.18.12:56:25 Info: m0: "fpga_ddr" instantiated altera_mem_if_ddr3_afi_mux "m0"
ERROR: Cannot find sequencer/sequencer.elf
2026.09.18.12:56:27 Error: s0: Cannot find sequencer/sequencer.elf
2026.09.18.12:56:27 Error: s0: An error occurred
while executing
"error "An error occurred""
(procedure "_error" line 8)
invoked from within
"_error "Cannot find $seq_file""
("if" then script line 2)
invoked from within
"if {[file exists $seq_file] == 0} {
_error "Cannot find $seq_file"
}"
(procedure "alt_mem_if::util::seq_mem_size::get_max_memory_usage" line 14)
invoked from within
"alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequencer" "sequencer.elf""
invoked from within
"set calc_mem_size [alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequencer" "sequencer.elf"]]"
("if" then script line 2)
invoked from within
"if { !$do_only_rw_mgr_mc && !($bfm_mode || $hps_mode)} {
set calc_mem_size [alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequenc..."
(procedure "generate_qsys_sequencer_sw" line 943)
invoked from within
"generate_qsys_sequencer_sw $prepend_str $protocol $pre_compile_dir $fileset $inhdl_dir $rdimm $lrdimm 0 0 $nios_hex_file_name $ac_rom_init_file_name ..."
invoked from within
"set seq_mem_size_list [generate_qsys_sequencer_sw $prepend_str $protocol $pre_compile_dir $fileset $inhdl_dir $rdimm $lrdimm 0 0 $nios_hex_file_name ..."
("if" else script line 2)
invoked from within
"if {[::alt_mem_if::util::qini::qini_value alt_mem_if_seq_size_request 0] > 0} {
set seq_mem_size [::alt_mem_if::util::qini::qini_value alt_mem_if_se..."
(procedure "alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer" line 238)
invoked from within
"alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer "${name}" $protocol $tmpdir $fileset {}"
invoked from within
"set qsys_sequencer_files_list [alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer "${name}" $protocol $tmpdir $fileset {}]"
(procedure "alt_mem_if::gen::uniphy_gen::generate_sequencer_files" line 3)
invoked from within
"alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "DDR3" $tmpdir QUARTUS_SYNTH"
invoked from within
"foreach generated_file [alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "DDR3" $tmpdir QUARTUS_SYNTH] {
set file_name [file tail $genera..."
(procedure "generate_synth" line 8)
invoked from within
"generate_synth dev_5cs_fpga_ddr_s0"
2026.09.18.12:56:27 Info: s0: "fpga_ddr" instantiated altera_mem_if_ddr3_qseq "s0"
2026.09.18.12:56:27 Error: Generation stopped, 241 or more modules remaining
2026.09.18.12:56:27 Info: dev_5cs: Done "dev_5cs" with 86 modules, 77 files
2026.09.18.12:56:30 Error: qsys-generate failed with exit code 1: 3 Errors, 12 Warnings
2026.09.18.12:56:30 Info: Finished: Create HDL design files for synthesis
make: *** [Makefile:263: stamp/qsys.stamp] Error 3

Please advise.
I know that WSL is set to Version 1
Thanks.

Bob N

MF RE: "Quick steps to Build" may be inaccurate in Building fpga 231 webpage - Added by Mike Fiorenza 2 days ago

Bob,

Can you provide the output of the following in WSL:

which wsl
which make
which dos2unix
wsl -l -v

Can you also provide the full log rather than the trimmed version? The part you cut is where qsys-generate reports how it invoked the Nios II shell, and that's the piece I'm missing.

- Mike

BN RE: "Quick steps to Build" may be inaccurate in Building fpga 231 webpage - Added by Bob Nayar 2 days ago

nayar@GDZTHGC4E:~$ which wsl
/usr/bin/wsl
nayar@GDZTHGC4E:~$ which make
/usr/bin/make
nayar@GDZTHGC4E:~$ which dos2unix
/usr/bin/dos2unix
nayar@GDZTHGC4E:~$ wsl -l -v
Unknown command: -l

When I do “wsl -l -v” from CMD window, I get:
NAME STATE VERSION

Ubuntu-20.04 Running 1
Ubuntu Stopped 2

Full logs:

nayar@GDZTHGC4E:/mnt/c/C10_CriticalLink/dev_5csx_h6_42a$ make all
qsys-generate dev_5cs.qsys --synthesis=VHDL
2026.09.18.14:37:13 Info: Saving generation log to /mnt/c/C10_CriticalLink/dev_5csx_h6_42a/dev_5cs/dev_5cs_generation.rpt
2026.09.18.14:37:13 Info: Starting: Create HDL design files for synthesis
2026.09.18.14:37:13 Info: qsys-generate /mnt/c/C10_CriticalLink/dev_5csx_h6_42a/dev_5cs.qsys --synthesis=VHDL --output-directory=/mnt/c/C10_CriticalLink/dev_5csx_h6_42a/dev_5cs/synthesis --family="Cyclone V" --part=5CSXFC6C6U23C7
2026.09.18.14:37:13 Info: Loading dev_5csx_h6_42a/dev_5cs.qsys
2026.09.18.14:37:13 Info: Reading input file
2026.09.18.14:37:13 Info: Adding check_0 [mem_check 1.0]
2026.09.18.14:37:13 Info: Parameterizing module check_0
2026.09.18.14:37:13 Info: Adding clk_100Mhz [clock_source 23.1]
2026.09.18.14:37:13 Info: Parameterizing module clk_100Mhz
2026.09.18.14:37:13 Info: Adding fpga_ddr [altera_mem_if_ddr3_emif 23.1]
2026.09.18.14:37:13 Info: Parameterizing module fpga_ddr
2026.09.18.14:37:13 Info: Adding hps_0 [altera_hps 23.1]
2026.09.18.14:37:13 Info: Parameterizing module hps_0
2026.09.18.14:37:13 Info: Adding mm_clock_crossing_bridge_0 [altera_avalon_mm_clock_crossing_bridge 23.1]
2026.09.18.14:37:13 Info: Parameterizing module mm_clock_crossing_bridge_0
2026.09.18.14:37:13 Info: Adding pio_0 [altera_avalon_pio 23.1]
2026.09.18.14:37:13 Info: Parameterizing module pio_0
2026.09.18.14:37:13 Info: Adding pio_1 [altera_avalon_pio 23.1]
2026.09.18.14:37:13 Info: Parameterizing module pio_1
2026.09.18.14:37:13 Info: Adding pio_2 [altera_avalon_pio 23.1]
2026.09.18.14:37:13 Info: Parameterizing module pio_2
2026.09.18.14:37:13 Info: Adding pio_3 [altera_avalon_pio 23.1]
2026.09.18.14:37:13 Info: Parameterizing module pio_3
2026.09.18.14:37:13 Info: Adding sysid_qsys [altera_avalon_sysid_qsys 23.1]
2026.09.18.14:37:13 Info: Parameterizing module sysid_qsys
2026.09.18.14:37:13 Info: Building connections
2026.09.18.14:37:13 Info: Parameterizing connections
2026.09.18.14:37:13 Info: Validating
2026.09.18.14:37:18 Info: Done reading input file
2026.09.18.14:37:19 Warning: dev_5cs.dev_5cs: Module dependency loop involving: "check_0" (mem_check 1.0), "hps_0" (altera_hps 23.1)
2026.09.18.14:37:19 Warning: dev_5cs.dev_5cs: Module dependency loop involving: "check_0" (mem_check 1.0), "hps_0" (altera_hps 23.1)
2026.09.18.14:37:19 Info: dev_5cs.check_0.wr: You have selected a length width that spans a larger transfer size than is addressable by the master port. Reducing the length width will improve the Fmax of this component.
2026.09.18.14:37:19 Warning: dev_5cs.check_0.rd_dis: Interrupt sender rd_dis.csr_irq is not connected to an interrupt receiver
2026.09.18.14:37:19 Warning: dev_5cs.check_0.wr_dis: Interrupt sender wr_dis.csr_irq is not connected to an interrupt receiver
2026.09.18.14:37:19 Warning: dev_5cs.fpga_ddr: ODT is disabled. Enabling ODT (Mode Register 1) may improve signal integrity
2026.09.18.14:37:19 Warning: dev_5cs.fpga_ddr: 'Quick' simulation modes are NOT timing accurate. Some simulation memory models may issue warnings or errors
2026.09.18.14:37:19 Warning: dev_5cs.fpga_ddr.pll_bridge: pll_bridge.pll_sharing cannot be both connected and exported
2026.09.18.14:37:19 Info: dev_5cs.hps_0: HPS Main PLL counter settings: n = 0 m = 63
2026.09.18.14:37:19 Info: dev_5cs.hps_0: HPS peripherial PLL counter settings: n = 0 m = 39
2026.09.18.14:37:19 Info: dev_5cs.hps_0: ECC will be enabled in the preloader because an interface width of 24 or 40 has been chosen.
2026.09.18.14:37:19 Info: dev_5cs.pio_0: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
2026.09.18.14:37:19 Info: dev_5cs.pio_1: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
2026.09.18.14:37:19 Info: dev_5cs.pio_2: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
2026.09.18.14:37:19 Info: dev_5cs.pio_3: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
2026.09.18.14:37:19 Info: dev_5cs.sysid_qsys: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID
2026.09.18.14:37:19 Info: dev_5cs.sysid_qsys: Time stamp will be automatically updated when this component is generated.
2026.09.18.14:37:19 Warning: dev_5cs.fpga_ddr: fpga_ddr.pll_sharing must be exported, or connected to a matching conduit.
2026.09.18.14:39:16 Info: dev_5cs: Generating dev_5cs "dev_5cs" for QUARTUS_SYNTH
2026.09.18.14:39:20 Info: Interconnect is inserted between master mm_clock_crossing_bridge_0.m0 and slave fpga_ddr.avl because the master has burstcount signal 1 bit wide, but the slave is 3 bit wide.
2026.09.18.14:39:20 Info: Interconnect is inserted between master mm_clock_crossing_bridge_0.m0 and slave fpga_ddr.avl because the master has address signal 28 bit wide, but the slave is 26 bit wide.
2026.09.18.14:39:20 Info: Interconnect is inserted between master mm_clock_crossing_bridge_0.m0 and slave fpga_ddr.avl because the master has byteenable signal 4 bit wide, but the slave is 0 bit wide.
2026.09.18.14:39:20 Info: Interconnect is inserted between master mm_clock_crossing_bridge_0.m0 and slave fpga_ddr.avl because the master has debugaccess signal 1 bit wide, but the slave is 0 bit wide.
2026.09.18.14:39:21 Warning: hps_0.f2h_irq0: Cannot connect clock for irq_mapper.sender
2026.09.18.14:39:21 Warning: hps_0.f2h_irq0: Cannot connect reset for irq_mapper.sender
2026.09.18.14:39:21 Warning: hps_0.f2h_irq1: Cannot connect clock for irq_mapper_001.sender
2026.09.18.14:39:21 Warning: hps_0.f2h_irq1: Cannot connect reset for irq_mapper_001.sender
2026.09.18.14:39:25 Info: check_0: "dev_5cs" instantiated mem_check "check_0"
2026.09.18.14:39:26 Info: fpga_ddr: "dev_5cs" instantiated altera_mem_if_ddr3_emif "fpga_ddr"
2026.09.18.14:39:26 Info: hps_0: "Running for module: hps_0"
2026.09.18.14:39:26 Info: hps_0: HPS Main PLL counter settings: n = 0 m = 63
2026.09.18.14:39:26 Info: hps_0: HPS peripherial PLL counter settings: n = 0 m = 39
2026.09.18.14:39:27 Info: hps_0: ECC will be enabled in the preloader because an interface width of 24 or 40 has been chosen.
2026.09.18.14:39:27 Info: hps_0: "dev_5cs" instantiated altera_hps "hps_0"
2026.09.18.14:39:27 Info: mm_clock_crossing_bridge_0: "dev_5cs" instantiated altera_avalon_mm_clock_crossing_bridge "mm_clock_crossing_bridge_0"
2026.09.18.14:39:27 Info: pio_0: Starting RTL generation for module 'dev_5cs_pio_0'
2026.09.18.14:39:27 Info: pio_0: Generation command is [exec /home/nayar/intelFPGA/23.1std/quartus/linux64/perl/bin/perl I /home/nayar/intelFPGA/23.1std/quartus/linux64/perl/lib -I /home/nayar/intelFPGA/23.1std/quartus/sopc_builder/bin/europa -I /home/nayar/intelFPGA/23.1std/quartus/sopc_builder/bin -I /home/nayar/intelFPGA/23.1std/quartus/../ip/altera/sopc_builder_ip/common -I /home/nayar/intelFPGA/23.1std/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio - /home/nayar/intelFPGA/23.1std/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=dev_5cs_pio_0 --dir=/tmp/alt0714_6377484093029951334.dir/0003_pio_0_gen/ --quartus_dir=/home/nayar/intelFPGA/23.1std/quartus --verilog --config=/tmp/alt0714_6377484093029951334.dir/0003_pio_0_gen//dev_5cs_pio_0_component_configuration.pl --do_build_sim=0 ]
2026.09.18.14:39:28 Info: pio_0: Done RTL generation for module 'dev_5cs_pio_0'
2026.09.18.14:39:28 Info: pio_0: "dev_5cs" instantiated altera_avalon_pio "pio_0"
2026.09.18.14:39:28 Info: pio_3: Starting RTL generation for module 'dev_5cs_pio_3'
2026.09.18.14:39:28 Info: pio_3: Generation command is [exec /home/nayar/intelFPGA/23.1std/quartus/linux64/perl/bin/perl I /home/nayar/intelFPGA/23.1std/quartus/linux64/perl/lib -I /home/nayar/intelFPGA/23.1std/quartus/sopc_builder/bin/europa -I /home/nayar/intelFPGA/23.1std/quartus/sopc_builder/bin -I /home/nayar/intelFPGA/23.1std/quartus/../ip/altera/sopc_builder_ip/common -I /home/nayar/intelFPGA/23.1std/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio - /home/nayar/intelFPGA/23.1std/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=dev_5cs_pio_3 --dir=/tmp/alt0714_6377484093029951334.dir/0004_pio_3_gen/ --quartus_dir=/home/nayar/intelFPGA/23.1std/quartus --verilog --config=/tmp/alt0714_6377484093029951334.dir/0004_pio_3_gen//dev_5cs_pio_3_component_configuration.pl --do_build_sim=0 ]
2026.09.18.14:39:29 Info: pio_3: Done RTL generation for module 'dev_5cs_pio_3'
2026.09.18.14:39:29 Info: pio_3: "dev_5cs" instantiated altera_avalon_pio "pio_3"
2026.09.18.14:39:29 Info: sysid_qsys: "dev_5cs" instantiated altera_avalon_sysid_qsys "sysid_qsys"
2026.09.18.14:39:30 Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
2026.09.18.14:39:30 Info: mm_interconnect_0: "dev_5cs" instantiated altera_mm_interconnect "mm_interconnect_0"
2026.09.18.14:39:32 Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
2026.09.18.14:39:32 Info: avalon_st_adapter_001: Inserting error_adapter: error_adapter_0
2026.09.18.14:39:32 Info: avalon_st_adapter_002: Inserting error_adapter: error_adapter_0
2026.09.18.14:39:32 Info: avalon_st_adapter_003: Inserting error_adapter: error_adapter_0
2026.09.18.14:39:32 Info: avalon_st_adapter_004: Inserting error_adapter: error_adapter_0
2026.09.18.14:39:32 Info: avalon_st_adapter_005: Inserting error_adapter: error_adapter_0
2026.09.18.14:39:32 Info: mm_interconnect_1: "dev_5cs" instantiated altera_mm_interconnect "mm_interconnect_1"
2026.09.18.14:39:33 Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
2026.09.18.14:39:33 Info: mm_interconnect_2: "dev_5cs" instantiated altera_mm_interconnect "mm_interconnect_2"
2026.09.18.14:39:33 Info: irq_mapper: "dev_5cs" instantiated altera_irq_mapper "irq_mapper"
2026.09.18.14:39:33 Info: irq_mapper_001: "dev_5cs" instantiated altera_irq_mapper "irq_mapper_001"
2026.09.18.14:39:33 Info: rst_controller: "dev_5cs" instantiated altera_reset_controller "rst_controller"
2026.09.18.14:39:33 Info: check: "check_0" instantiated altera_avalon_data_pattern_checker "check"
2026.09.18.14:39:33 Info: csr: "check_0" instantiated altera_avalon_mm_bridge "csr"
2026.09.18.14:39:33 Info: gen: "check_0" instantiated altera_avalon_data_pattern_generator "gen"
2026.09.18.14:39:33 Info: rd: "check_0" instantiated dma_read_master "rd"
2026.09.18.14:39:34 Info: rd_dis: "check_0" instantiated modular_sgdma_dispatcher "rd_dis"
2026.09.18.14:39:34 Info: wr: "check_0" instantiated dma_write_master "wr"
2026.09.18.14:39:35 Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
2026.09.18.14:39:35 Info: mm_interconnect_0: "check_0" instantiated altera_mm_interconnect "mm_interconnect_0"
2026.09.18.14:39:37 Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
2026.09.18.14:39:37 Info: avalon_st_adapter_001: Inserting error_adapter: error_adapter_0
2026.09.18.14:39:37 Info: avalon_st_adapter_002: Inserting error_adapter: error_adapter_0
2026.09.18.14:39:37 Info: avalon_st_adapter_003: Inserting error_adapter: error_adapter_0
2026.09.18.14:39:37 Info: mm_interconnect_1: "check_0" instantiated altera_mm_interconnect "mm_interconnect_1"
2026.09.18.14:39:38 Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
2026.09.18.14:39:38 Info: avalon_st_adapter_001: Inserting error_adapter: error_adapter_0
2026.09.18.14:39:38 Info: avalon_st_adapter_002: Inserting error_adapter: error_adapter_0
2026.09.18.14:39:38 Info: mm_interconnect_2: "check_0" instantiated altera_mm_interconnect "mm_interconnect_2"
2026.09.18.14:39:39 Info: pll0: "fpga_ddr" instantiated altera_mem_if_ddr3_pll "pll0"
2026.09.18.14:39:39 Info: p0: Generating clock pair generator
2026.09.18.14:39:40 Info: p0: Generating dev_5cs_fpga_ddr_p0_altdqdqs
2026.09.18.14:39:59 Info: p0:
2026.09.18.14:39:59 Info: p0: *********************
2026.09.18.14:39:59 Info: p0:
2026.09.18.14:39:59 Info: p0: Remember to run the dev_5cs_fpga_ddr_p0_pin_assignments.tcl
2026.09.18.14:39:59 Info: p0: script after running Synthesis and before Fitting.
2026.09.18.14:39:59 Info: p0:
2026.09.18.14:39:59 Info: p0: *********************
2026.09.18.14:39:59 Info: p0:
2026.09.18.14:39:59 Info: p0: "fpga_ddr" instantiated altera_mem_if_ddr3_phy_core "p0"
2026.09.18.14:39:59 Info: m0: "fpga_ddr" instantiated altera_mem_if_ddr3_afi_mux "m0"
ERROR: Cannot find sequencer/sequencer.elf
2026.09.18.14:40:01 Error: s0: Cannot find sequencer/sequencer.elf
2026.09.18.14:40:01 Error: s0: An error occurred
while executing
"error "An error occurred""
(procedure "_error" line 8)
invoked from within
"_error "Cannot find $seq_file""
("if" then script line 2)
invoked from within
"if {[file exists $seq_file] == 0} {
_error "Cannot find $seq_file"
}"
(procedure "alt_mem_if::util::seq_mem_size::get_max_memory_usage" line 14)
invoked from within
"alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequencer" "sequencer.elf""
invoked from within
"set calc_mem_size [alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequencer" "sequencer.elf"]]"
("if" then script line 2)
invoked from within
"if { !$do_only_rw_mgr_mc && !($bfm_mode || $hps_mode)} {
set calc_mem_size [alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequenc..."
(procedure "generate_qsys_sequencer_sw" line 943)
invoked from within
"generate_qsys_sequencer_sw $prepend_str $protocol $pre_compile_dir $fileset $inhdl_dir $rdimm $lrdimm 0 0 $nios_hex_file_name $ac_rom_init_file_name ..."
invoked from within
"set seq_mem_size_list [generate_qsys_sequencer_sw $prepend_str $protocol $pre_compile_dir $fileset $inhdl_dir $rdimm $lrdimm 0 0 $nios_hex_file_name ..."
("if" else script line 2)
invoked from within
"if {[::alt_mem_if::util::qini::qini_value alt_mem_if_seq_size_request 0] > 0} {
set seq_mem_size [::alt_mem_if::util::qini::qini_value alt_mem_if_se..."
(procedure "alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer" line 238)
invoked from within
"alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer "${name}" $protocol $tmpdir $fileset {}"
invoked from within
"set qsys_sequencer_files_list [alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer "${name}" $protocol $tmpdir $fileset {}]"
(procedure "alt_mem_if::gen::uniphy_gen::generate_sequencer_files" line 3)
invoked from within
"alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "DDR3" $tmpdir QUARTUS_SYNTH"
invoked from within
"foreach generated_file [alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "DDR3" $tmpdir QUARTUS_SYNTH] {
set file_name [file tail $genera..."
(procedure "generate_synth" line 8)
invoked from within
"generate_synth dev_5cs_fpga_ddr_s0"
2026.09.18.14:40:01 Info: s0: "fpga_ddr" instantiated altera_mem_if_ddr3_qseq "s0"
2026.09.18.14:40:01 Error: Generation stopped, 241 or more modules remaining
2026.09.18.14:40:01 Info: dev_5cs: Done "dev_5cs" with 86 modules, 77 files
2026.09.18.14:40:02 Error: qsys-generate failed with exit code 1: 3 Errors, 12 Warnings
2026.09.18.14:40:02 Info: Finished: Create HDL design files for synthesis
make: *** [Makefile:263: stamp/qsys.stamp] Error 3

MF RE: "Quick steps to Build" may be inaccurate in Building fpga 231 webpage - Added by Mike Fiorenza 2 days ago

Bob,

Thanks for the log, I think this narrowed down your issue. Your Quartus is a Linux install running inside WSL, and Altera's nios2_command_shell.sh assumes WSL means a Windows install, so it puts the mingw32 toolchain on your PATH instead of the Linux one. Those directories don't exist in your install, so nios2-elf-gcc never gets found and the sequencer build silently produces nothing.

Launch the Nios II shell, then run the following:

which nios2-elf-gcc

My guess is this won't resolve. So export the following:

export PATH=$SOPC_KIT_NIOS2/bin/gnu/H-x86_64-pc-linux-gnu/bin:$PATH

Then run the following again:

which nios2-elf-gcc

This should now hopefully resolve. Then you can continue with the build.
- Mike

BN RE: "Quick steps to Build" may be inaccurate in Building fpga 231 webpage - Added by Bob Nayar 2 days ago

Actually, Mike.
I have Quartus 23.1 installed in both WSL and my Windows
The WSL install is in /home/nayar/intelFPGA/23.1 and the Windows install is in C:\intelFPGA\23.1std

and so, when I go a "which nios2-elf-gcc", I do get the correct resolved path:

nayar@GDZTHGC4E:/mnt/c/C10_CriticalLink/dev_5csx_h6_42a$ which nios2-elf-gcc
/home/nayar/intelFPGA/23.1std/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/nios2-elf-gcc

So yeah, even after the export PATH commmand, I get the same issue

Bob N

MF RE: "Quick steps to Build" may be inaccurate in Building fpga 231 webpage - Added by Mike Fiorenza 2 days ago

Bob,

The following is my guess:

You needed WSL 1 for the Windows Quartus Nios II shell, but now that you've moved to a Linux Quartus install inside WSL, WSL 1 is likely working against you. You already have an Ubuntu distro on WSL 2, so it may be worth trying the Linux build over there.

- Mike

BN RE: "Quick steps to Build" may be inaccurate in Building fpga 231 webpage - Added by Bob Nayar 2 days ago

Mike, when you asked to do this command:

which nios2-elf-gcc

did you mean "which nios2-elf-gcc. exe " ?

Bob N

BN RE: "Quick steps to Build" may be inaccurate in Building fpga 231 webpage - Added by Bob Nayar 2 days ago

I am asking that because

"which nios2-elf-gcc" gives me nothing

but "which nios2-elf-gcc.exe" gives me /mnt/c/intelFPGA/23.1std/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/nios2-elf-gcc.exe

Same for "Which quartus.exe".

Is this a clue?

BN RE: "Quick steps to Build" may be inaccurate in Building fpga 231 webpage - Added by Bob Nayar 1 day ago

I re-installed WSL (deleting the Linux Quartus install), this time using Ubuntu 22.04
(I did not have the option of installing Ubuntu 20 and CriticalLink's website says that 22 is OK)

Try to start from the beginning now, because I want to document the steps.

I was able to progress in 'generate_from_tcl' by adding '.exe' to the tail of the following executables in the Makefile:
quartus_sh
qsys-script

My next question is:
Can these error messages below be ignored during the 'generate_from_tcl' process?:

ERROR: Device family can not be determined
ERROR: The minimum delay difference between CK and DQS must be less than or equal to the maximum delay difference between CK and DQS
Error: set_interface_property hps_io EXPORT_OF hps_0.hps_io: No interface named hps_0.hps_io.

Trying to see if these errors are causing the 'generate_from_tcl' process to fail like this:
make¹: * [Makefile:563: qsys_generate_qsys] Error 1
make¹: Leaving directory '/mnt/c/C10_CriticalLink/dev_5csx_h6_42a'
make: * [Makefile:575: generate_from_tcl] Error 2

Nevertheless, the QSYS file(s) are still generated

BN RE: "Quick steps to Build" may be inaccurate in Building fpga 231 webpage - Added by Bob Nayar about 1 hour ago

Another that I get during 'generate_from_tcl' is:

Error: set_project_property DEVICE '5CSXFC6C6U23C7': The device '5CSXFC6C6U23C7' is unknown; reverted to the default device.

This error does not make my sense to me.
The consequences of this error seen when I do a 'make all' from this point on and I see this error:

Error: hps_0: Selected device '5CEBA2F17A7' is not an SoC device. Please choose a valid SoC device to use the Hard Processor System.

I don't know why I am getting the The device '5CSXFC6C6U23C7' is unknown error in the first place.

(1-11/11)

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BN"Quick steps to Build" may be inaccurate in Building fpga 231 webpage

Replies (11)

MF RE: "Quick steps to Build" may be inaccurate in Building fpga 231 webpage - Added by Mike Fiorenza 3 days ago

BN RE: "Quick steps to Build" may be inaccurate in Building fpga 231 webpage - Added by Bob Nayar 2 days ago

MF RE: "Quick steps to Build" may be inaccurate in Building fpga 231 webpage - Added by Mike Fiorenza 2 days ago

BN RE: "Quick steps to Build" may be inaccurate in Building fpga 231 webpage - Added by Bob Nayar 2 days ago

MF RE: "Quick steps to Build" may be inaccurate in Building fpga 231 webpage - Added by Mike Fiorenza 2 days ago

BN RE: "Quick steps to Build" may be inaccurate in Building fpga 231 webpage - Added by Bob Nayar 2 days ago

MF RE: "Quick steps to Build" may be inaccurate in Building fpga 231 webpage - Added by Mike Fiorenza 2 days ago

BN RE: "Quick steps to Build" may be inaccurate in Building fpga 231 webpage - Added by Bob Nayar 2 days ago

BN RE: "Quick steps to Build" may be inaccurate in Building fpga 231 webpage - Added by Bob Nayar 2 days ago

BN RE: "Quick steps to Build" may be inaccurate in Building fpga 231 webpage - Added by Bob Nayar 1 day ago

BN RE: "Quick steps to Build" may be inaccurate in Building fpga 231 webpage - Added by Bob Nayar about 1 hour ago