Activity
From 08/18/2010 to 09/16/2010
09/16/2010
- 08:26 PM Software Development: RE: LCD/Display questions
- I'll need a little more information about the uboot to be able to have it tell the kernel to initialize the device. A...
- 07:01 PM Software Development: RE: LCD/Display questions
- Mr. Schlunk,
The kernel included in the development kit provided should have the necessary code installed to suppo... - We are trying to figure out how to get video out of the board and had a couple of questions.
Does your development... - I need to implement a data bus as part of an interface to the Xilinx FPGA, and it must be a bidirectional BLVDS inter...
09/07/2010
- 04:12 PM FPGA Development: RE: Critical link bit file
- Actually John,
you shouldn't need to reprogram the NAND/root filesystem. Only the kernel. The NAND should still ... - 04:10 PM FPGA Development: RE: Critical link bit file
- Right. The procedure you just ran only reloads the bootloader images.
You will also need to reload the kernel i... - 04:03 PM FPGA Development: RE: Critical link bit file
- it gets into uboot but once past uboot I get this
8192 KiB M25P64 at 0:0 is now current device
Wrong Image Format... - 04:01 PM FPGA Development: RE: Critical link bit file
- that worked I am backup and running.
thanks
John - 03:52 PM FPGA Development: RE: Critical link bit file
- Hi John,
I copied the instructions wrong from our factory programming instruations. Sorry. The "-c" option shoul... - 03:43 PM FPGA Development: RE: Critical link bit file
- I ran this exactly how you said and I get the usage for the command here is what I typed in
sfh_OMAP-L138 -flash ... - 01:38 PM FPGA Development: RE: Critical link bit file
- Look at the [[Reprogramming a Dead Board]] wiki link. Let me know if you run into trouble.
-Mike
- 01:18 PM FPGA Development: RE: Critical link bit file
- It was my fault not yours so no big deal. If you can post what it takes to re-flash the boot code. If this doesn't...
- 07:54 AM FPGA Development: RE: Critical link bit file
- Hi John,
Well, the bad news is that I think you whacked the bootloading code on the SPI FLASH.
The "sf write" c... - 07:57 AM Software Development: RE: Audio help needed
- Hi Otmar,
The API will be ALSA.
My best guess would be something mid-October. We'll try to bump it up on the p...
09/03/2010
- 06:40 PM FPGA Development: RE: Critical link bit file
- Nothing at all unless I hit both buttons and then I see BOOTME.
here is the console after doing the Kermit upload
... - 06:35 PM FPGA Development: RE: Critical link bit file
- Do you have a text capture of the commands you typed?
You need to be careful executing commands that write to the ... - 06:32 PM FPGA Development: RE: Critical link bit file
OK I went through all of that and now my platform does not boot at all. no text coming across on the serial port. ...- 04:14 PM FPGA Development: RE: Critical link bit file
- Sorry, tftp is network transfer protocol. Didn't know you weren't on the network.
If you would like to transfer t... - 03:47 PM FPGA Development: RE: Critical link bit file
- Why would I have q network cable plugged in and what to I plug it into? My home network? I am using the serial por...
- 03:38 PM FPGA Development: RE: Critical link bit file
- This usually means that the network cable isn't plugged in or the other end isn't talking.
- 03:09 PM FPGA Development: RE: Critical link bit file
- When trying to load the FPGA through Uboot I get this error
T WARN: emac_send_packet: No link
T WARN: emac_send... - 02:57 PM FPGA Development: RE: Critical link bit file
- It looks like it works once I tri-stated the wait signals I can not reproduce the problem.
I sent a new file to ou... - 01:22 PM FPGA Development: RE: Critical link bit file
- We only use CS2 and the IO_EMA_D bus is only driven when CS2 and OE are active.
I have the wait signals driven h... - 11:26 AM FPGA Development: RE: Critical link bit file
- Also, if you'd like to send me your project file (offline, if you'd prefer) we could arrange that. Then we can at le...
- 11:24 AM FPGA Development: RE: Critical link bit file
- John. Quick question: which chip select space are you using to talk to the FPGA? We have wired all of them over to...
- Can you send me the bin and bit file for your FPGA. I am trying to debug the crash that happens when we program our...
08/31/2010
- 07:06 PM Software Development: RE: Audio help needed
- Hi Mike,
Thank you for the information.
Once the drivers exist -- would you know what API I should probably be... - 05:20 PM Software Development: RE: Audio help needed
- Hello Mr. Schlunk,
Unfortunately, in order to use the audio output a new sound "board/driver" needs to be written ... - 04:08 PM FPGA Development: RE: FPGA Unused Pins
- Thanks
- 03:47 PM FPGA Development: RE: FPGA Unused Pins
- Hi John,
In general, you should tri-state / float all unused pins on the FPGA. This will result in those pins beh... - Did you have to do anything special to the unused EMIFA pins like
I_EMA_CS0_N
I_EMA_CS3_N
I_EMA_CS5_N
I_EMA_CAS... - 04:05 PM FPGA Development: RE: Digital DNA
- Yes but I think the range of the DNA value is assigned per customer so each customer has a unique set of values and n...
- 03:53 PM FPGA Development: RE: Digital DNA
- Stuff you probably already know, but:
According to our distributor, the Xilinx DNA code is unique per chip (like a...
08/30/2010
- I'm trying to figure out a simple method of getting a sound file to play on the board from our app.
After looking ... - 02:36 PM FPGA Development: RE: Accessing the FPGA Memory space using U-boot
- Hey I figured it out so never mind. the FPGA is at 0x6000000 and the memory commands in Uboot seem to work.
- I sent this messge to our software guys also but if youcan help it would be appreciated.
In order to debug the F... - 01:37 PM FPGA Development: RE: Digital DNA
- We do no need it on the MityDSP board I was just curious. We are using it on our PROBE FPGA. If you had one assigne...
08/27/2010
- 03:37 PM FPGA Development: RE: Digital DNA
- Hi John,
We're still looking into this here (I wanted to at least get you some feedback that someone saw your post...
08/26/2010
- Did you get a digital DNA value assigned for your FPGA's?
08/24/2010
- 09:11 PM FPGA Development: RE: POWER DOWN Memory Corruption
If your application will not be writing to the NAND flash then you should not need hold-up circuit from the motherb...- 09:04 PM FPGA Development: RE: POWER DOWN Memory Corruption
- So do you think we need to put on our mother board a circuit to hold up the power and interrupt the OMAP to let it kn...
- 08:58 PM FPGA Development: RE: POWER DOWN Memory Corruption
- John -
We are indeed aware of this and are working on a solution. We plan to allow for the root file system to be... - Software guys tell me they had a case where the FLASH memory was corrupted when the power was removed at the wrong ti...
- 06:51 PM FPGA Development: RE: Programming the FPGA
Hi John.
It looks like you are generating the .BIN file using the bitgen tool ("Generate Programming File" step ...- 04:00 PM FPGA Development: RE: Programming the FPGA
- Here is the .BGN but there were no .CFI or .PRM files in the FPGA directory.
- 03:44 PM FPGA Development: RE: Programming the FPGA
Hi John.
Would you be able to upload the .BGN .CFI & .PRM files that go with the .BIN file you have already uplo...- We are using the MityDSP-L138. Our software guys are not able to program my FPGA bin file using your routine. Your ...
08/23/2010
- 02:34 PM Software Development: RE: Rescanning the Nand flash
- Dennis,
Just so you know, the suggestions below are not based on personal experience.
Not sure there is a comma... - I made a type-o when loading the Nand flash. I managed to convince the flash that it has a whole bunch of bad areas. ...
08/18/2010
- 04:16 PM Software Development: RE: Loading FPGA
- Yes it is an industrial i/o board. That file did load, the light did come on. I need to tell the fpga guys they gave ...
- 03:46 PM Software Development: RE: Loading FPGA
- If you are using the Industrial I/O board Critical Link provided, try using the file attached below. This file is kn...
- 03:35 PM Software Development: RE: Loading FPGA
- Sorry about the typo-s. My email/web machine doesn't have a serial port so I've got an old laptop running the hyperte...
- 03:16 PM Software Development: RE: Loading FPGA
- On the tftp, what is the reported size of the transfer? Something like 0x71544 is expected. If the data is not the ri...
- 03:08 PM Software Development: RE: Loading FPGA
- I did tftp: 0xC0700000 192.168.1.118:fpga.bin
got the ### marks
Did
loadfpga 0xC07000000
no light, message "... - 02:58 PM Software Development: RE: Loading FPGA
- Yes, the "done" LED should light up when the FPGA is programmed correctly.
Can you include the set of commands you... - 02:51 PM Software Development: RE: Loading FPGA
- Should the "done" LED light up if the FPGA was programmed correctly?
- 02:39 PM Software Development: RE: Loading FPGA
- Dennis,
You are correct that the write command is missing the offset.
In the setenv command, the read is corre... - I've tried loading the FPGA. I didn't write the FPGA code, I'm just trying to load an fpga.bin file that I've been gi...
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