Activity
From 08/07/2012 to 09/05/2012
09/05/2012
- MW 03:03 PM Software Development: RE: L138 SD Card Boot & AISgen
- I don't have a bunch of time to wander off on this, but you might check the the DEVICE_INIT() routine of the $MDK/sw/3rdparty/OMAP-L138_FlashAndBootUtils_2_27/OMAP-L138/Common/src/device.c file. This has the PLL and DDR initialization c...
- RM 02:44 PM Software Development: RE: L138 SD Card Boot & AISgen
- Hi Mike,
Thanks for getting back to me so quickly.
We are indeed using a non-FPGA SOM. We have DIP switches on our baseboard to let us set the Boot[4..1] pins and changing these certainly changes the boot behaviour. Pull-ups are 1k... - MW 01:15 PM Software Development: RE: L138 SD Card Boot & AISgen
- Hi Richard,
Can you confirm you using a SOM without an FPGA?
FPGA based SOMs do not expose the bootmode / bootconfig pins necessary to boot directly out of SD. Those modules only support booting from SPI NOR or from UART via the... - Hi,
We're trying to create an SD card that contains both u-boot and our Linux kernel for an L138 module. We've now got our own baseboard, but it is very similar to the IndustrialIO board.
I've read the TI wiki pages on SD boot (htt...
09/04/2012
- EB 04:32 PM FPGA Development: RE: Voltage of bank 3 on MityARM 1810F
- Thanks for the quick reply!
- MW 04:16 PM FPGA Development: RE: Voltage of bank 3 on MityARM 1810F
- No that is a typo in the UCF file. The voltage is really 1.8V.
Those lines in the UCF should be as shown below. I thought we had corrected that in the BSP packages, looks like the errors are still there. Sorry Emmett. - EB 03:58 PM FPGA Development: RE: Voltage of bank 3 on MityARM 1810F
- Are these lines truly connect to the AM1808 as implied in the UCF?
- I started my FPGA code using fpga/vhdl/MityDSP_L138.ucf
I want to add to the design io_gp8(15 downto 8).
These lines are commented out in MityDSP_L138.ucf but the IO is 1.8V.
NET "io_gp8<15>" LOC = "T1" | IOSTANDARD = LVCMOS18;
1....
08/31/2012
- JP 09:58 AM Software Development: RE: Debugging DSP in VirtualBox?
- The Spectrum Digital XDS510 USB emulator pod does not seem to be useable from within the current Oracle VirtualBox.
08/30/2012
I followed the procedures of "Installing Open Embedded Core", no problem from step 1 to 4, but at step 5, there's no ~/.oe/environment-oecore file, how to create the file?
I flashed Angstrom v2012.05 - Kernel 3.2.0 to my mitydspL138...
08/28/2012
- CO 07:08 AM PCB Development: RE: MMCSD
- Sorry, I meant GPIO_0[6 or 7 or 13 or 15] as they are on the J700 connector along with MMCSD0...
- CO 04:16 AM PCB Development: RE: MMCSD
- Ah yes, that makes sense - I forgot about the degree of pin muxing going on in the L138 and the UPP would make sense there. My design is based around the WL1271 as well actually, although I've no reason to suppose a TXB0108 wouldn't do t...
08/27/2012
- MW 07:06 PM PCB Development: RE: Used EMIFA-Signals/Pins
- Yes, there should be several.
The only interface on the EMA on the modules with non-FPGA pins is the NAND (x8, but the upper 8 bit lines should probably be left alone). The NAND interface uses the following signals:
EMA_D(15..0)
... - CR 06:48 PM PCB Development: RE: Used EMIFA-Signals/Pins
- This is the mainquestion: Are there some not used Pins of the EMA interface which i can use as GPIO and keep the onboard memory working at the same time?
I need the GPIOs on the EMA-Pins, because i wanna connect some devices to the dev-... - MW 11:13 AM Software Development: RE: Vision Development Kit - What toolchain?
- Any of the ARM side GCC toolchains released should work with the VDK. I would recommend using the most recent one distributed.
The DSP side, I believe, was compiled with CGT 6.1.19, but any version 7.0 chain should work.
-Mike
- MW 10:28 AM PCB Development: RE: MMCSD
- Hello Conor,
Some background: the MMCSD1 was routed through the FPGA because it is pin-muxed with the UPP channel 0, which gets used quite a bit by our customers to push acquisition data from the FPGA into the OMAP-L138 processor. Ou... - Hi all,
I was looking at interfacing a wireless module to the MMCSD ports on the MityDSP L138F module. There are two ports available - one out to the dev board and one to the FPGA. The dev board is 3.3V LVCMOS but the module I have in...
08/23/2012
- CR 04:12 PM PCB Development: RE: Used EMIFA-Signals/Pins
- The one without the FPGA.
- MW 12:42 PM PCB Development: RE: Used EMIFA-Signals/Pins
- For which module? One that includes an FPGA or not?
- Hi,
which EMA-Pins of the EMIFA-Interface already connected to the L138-onboard-peripherials?
I couldn't found any detaild informations about.
Thanks,
Christian - WC 09:05 AM PCB Development: RE: MityDSP-L138F Mounting Holes (Posted on behalf of a customer)
- Mike, thanks for the quick response.
A STEP model is currently available at [http://support.criticallink.com/redmine/attachments/1293/MityDSP-L138F.step] unless you're referring to a newer version.
The keep-out area shown in the d... - MW 08:36 AM PCB Development: RE: MityDSP-L138F Mounting Holes (Posted on behalf of a customer)
- We may have a STEP model of the module, let me see if I can get that published.
- MW 08:35 AM PCB Development: RE: MityDSP-L138F Mounting Holes (Posted on behalf of a customer)
- Short answer is yes, 1.6mm maximum height. And you should probably hold to that height for the entire area below SOM as per the design guide, as there are a couple of small IC's outside the area in the drawing that was posted and there ...
- WC 08:11 AM PCB Development: RE: MityDSP-L138F Mounting Holes (Posted on behalf of a customer)
- The drawing you provided highlights a keep-out area for high profile components. What is the maximum component height allowed in this area? Is it 1.60 mm as specified in Figure 2 of the carrier board design guide?
Thanks.
08/22/2012
- Can JTAG debugging be performed from within CCS running in a VirtualBox?
- What GCC toolchain is used to build the VDK Linux application? DSP?
08/14/2012
- MW 03:08 PM Software Development: RE: L138 - DSP Timer interrupt question ...
- Are you running DSPLINK to load/run program the C674x side?
DSPLINK uses interrupt levels 4 and 5 for the ARM/DSP IPC. You might try using a level above 5 for the interrupt, particularly if you are seeing sporadic interrupt behavior.... - (posted on behalf of a customer)
We are running on the board on the C674x side and have some success with our periodic timer interrupt. However, it seems we are not setting up the interrupt controller properly since we sometimes get p...
08/11/2012
- MW 08:18 AM Software Development: RE: General SW questions on the MityDSP L138F development kit
- Hi Greg,
At the risk of writing a novel, I recommend you take a peek at the following pages / sites / documents:
- "MityDSP-L138F DataSheet":http://www.mitydsp.com/images/upload/File/MityDSP-L138F%20Spec.pdf
- "MityDSP-L138F Archi...
08/10/2012
- A few general SW questions for the novice user. We are planning to use the MityDSP L138F development kit. Here are some general questions:
1. Can our development SW code run out of FLASH?
2. If not, what is the footprint our deve...