Mity CPU Platforms » MityDSP-L138 (ARM9 Based Platforms)

07/20/2016

03:21 PM FPGA Development: RE: Communication EGD or ModBus/TCP Cores

Hector,
I spoke with Jon C. about this issue and we have a little more followup.
In the past for the MitySOM/DS... Alexander Block

10:16 AM FPGA Development: RE: Communication EGD or ModBus/TCP Cores

Hector Bojorquez wrote:
> Hi,
>
> I'm a beginner with FPGA and embedded systems, now I'm creating a communication... Jonathan Cormier

09:42 AM FPGA Development: Communication EGD or ModBus/TCP Cores

Hi,
I'm a beginner with FPGA and embedded systems, now I'm creating a communication between some devices and the M... Hector Bojorquez

07/12/2016

09:02 AM Software Development: RE: SPI1 controller, access to FLASH and carrier board. NOT linux based.

Excellent glad you got it working. Jonathan Cormier

12:16 AM Software Development: RE: SPI1 controller, access to FLASH and carrier board. NOT linux based.

Johnathan,
Joy Joy, Happy Happy.
Everything is working. There were three items altogether. First was the "open... Ian St. John

07/11/2016

05:06 PM Software Development: RE: L138 dsplink problem - schedule while atomic bug

I looked deeper into the error we were provoking on our bench; it turned out to be a c++ vector de-referencing error ... Fred Weiser

07/09/2016

06:24 PM Software Development: RE: SPI1 controller, access to FLASH and carrier board. NOT linux based.

Ian St. John wrote:
> Can you confirm that the signal marked as 'reserved' just beside the SPI1_CSC1 is the SPI1_CSC... Jonathan Cormier

05:56 PM Software Development: RE: SPI1 controller, access to FLASH and carrier board. NOT linux based.

Hmm. I asked the EE about the diagram and he was interested in the fact that there was a pull up on the CS line. Appa... Ian St. John

12:40 AM Software Development: RE: SPI1 controller, access to FLASH and carrier board. NOT linux based.

The eeprom is on the i2c0 bus. I'm assuming you are talking about the SPI Nor flash which is on SPI1_CS0.+
Oops... Ian St. John

01:23 PM Software Development: RE: L138 dsplink problem - schedule while atomic bug

Hi Fred,
Syslink is newer than DSPlink, though in the context of the L138 it's very similar code (syslink evolved ... Michael Williamson

12:11 PM Software Development: RE: L138 dsplink problem - schedule while atomic bug

The error collected above was on the bench after making some minor software changes seemingly unrelated with the code... Fred Weiser

11:23 AM Software Development: RE: L138 dsplink problem - schedule while atomic bug

I found the following on the TI site; looks like they struggled with this issue with sys-link... I'm not sure how sys... Fred Weiser

07/08/2016

11:55 AM Software Development: L138 dsplink problem - schedule while atomic bug

I think there may be a bug in the dsplink kernel code that causes the scheduler to run after a call to spinlock. "rem... Fred Weiser

09:33 AM Software Development: RE: SPI1 controller, access to FLASH and carrier board. NOT linux based.

Ian St. John wrote:
> I am building and programming a custom board without Linux. Basic embedded drivers running fro... Jonathan Cormier

07/05/2016

10:18 AM Software Development: SPI1 controller, access to FLASH and carrier board. NOT linux based.

I am building and programming a custom board without Linux. Basic embedded drivers running from SPI1,CS0 (8MB NOR Fla... Ian St. John

06/22/2016

04:13 AM Software Development: RE: kernel 3.2 - tcpip stack latency

Hi Greg,
Than you for your feedback.
Indeed, flag CONFIG_PREEMPT is set in kernel config. As far as we can see... Patrice Bastiaens

06/21/2016

01:30 PM Software Development: RE: kernel 3.2 - tcpip stack latency

Hi Patrice,
Since you are using SCHED_RR I am assuming you are using CONFIG_PREEMPT in your kernel config, correc... Gregory Gluszek

06:26 AM Software Development: kernel 3.2 - tcpip stack latency

Hello,
We've built an application receiving messages from two devices at a rate of 1 message of 1440 bytes every 1... Patrice Bastiaens