Activity

From 12/05/2011 to 01/03/2012

08:20 AM PCB Development: RE: FPGA/DSP Interface Details & external interrupts: Doug -
I will let the technical team answer the question about the external interrupts. However, we will add info... Thomas Catalino
08:16 AM PCB Development: FPGA/DSP Interface Details & external interrupts: (Posted on behalf of a customer)
I am working on designing the carrier interface board for the MityDSP Pro module.... Thomas Catalino

09:45 AM PCB Development: RE: MityDSP-Pro FPGA questions ...: > In the directory labeled “C:\MityDSP\2.10\hardware\FPGA_boot” I see several sub directories that appear to have pre... Michael Williamson

11:53 AM PCB Development: RE: MityDSP-Pro FPGA questions ...: (from Anthony)
Michael,

Thanks for the response. From what you describe it seems that the signals I intend to... Thomas Catalino

07:16 PM PCB Development: RE: MityDSP-Pro FPGA questions ...: Hi Tom / Anthony,
I hope this doesn't muddy the waters, but here is some more information: There are actually 3 E... Michael Williamson
01:01 PM PCB Development: RE: MityDSP-Pro FPGA questions ...: ??From the schematics it appears that the evaluation board is connected to both RJ-45 connectors, one goes to the 10/... Thomas Catalino
11:04 AM PCB Development: RE: MityDSP-Pro FPGA questions ...: Hello Tom,
I will try posting this to the support forum as well but I need to clear up some confusion Kevin and I ... Anthony Medina

02:35 PM PCB Development: RE: MityDSP-Pro FPGA questions ...: The bootloader FPGA image included in the file mention provides a basic UART at pins 14 and 16 of the edge connector ... Michael Williamson

06:13 PM PCB Development: MityDSP-Pro FPGA questions ...: (posted on behalf of a customer)
RS232_TXD SO-DIMM pin 14
RS232_RXD SO-DIMM pin 16

F... Thomas Catalino

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