Activity
From 11/25/2013 to 12/24/2013
12/12/2013
- 06:56 PM FPGA Development: RE: ASADSn / ASREn pin loc
- EMIF_ASADS# is routed to Y16, bank 4.
-Mike
- Hi,
Is the EMIFA signal ASADSn/ASREn routed to the FPGA? If so, what is the pin location?
I'm using the MityDSP... - 05:48 PM FPGA Development: RE: Additional Address Lines EA[19 downto 10] pin loc
- Thanks
- 05:47 PM FPGA Development: RE: Additional Address Lines EA[19 downto 10] pin loc
- Hi Leon,
Here are the rest of the EMIF_AEA pin assignments.
-Mike
| NET | FPGA PIN | FPGA BANK |
|... - 04:48 PM FPGA Development: RE: Additional Address Lines EA[19 downto 10] pin loc
- Hi,
Sorry, I'm using the MityDSP-Pro, 6455-JE-3X5-R.
Cheers,
Leon - 07:08 AM FPGA Development: RE: Additional Address Lines EA[19 downto 10] pin loc
- Hi Leon,
While module are you using? Do you have a model number or a part number?
-Mike
12/11/2013
- Hi,
In the supplied ucf files I can only find pin information for address lines i_emif_aea[9 downto 0]. I would li...
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