Activity
From 06/25/2014 to 07/24/2014
07/24/2014
- 09:05 AM FPGA Development: RE: FPGA DDR3 on 5CSX-H6-42A-RC-X (DDR)
- Hi Nigel,
I don't believe there is a way to do it directly in QSYS. You may be able to patch your generated outpu... - 07:59 AM FPGA Development: RE: FPGA DDR3 on 5CSX-H6-42A-RC-X (DDR)
- Hi Adam,
Thanks for the insights.
Do you know how to persuade qsys to run the DDR at a slower speed? In normal ...
07/23/2014
- 04:19 PM FPGA Development: RE: FPGA DDR3 on 5CSX-H6-42A-RC-X (DDR)
- Hi Nigel,
You are correct, the C8ES devices do not meet timing with the FPGA DDR according to Quartus. The ES sil... - Although your reference design using FPGA DDR compiles as supplied, when I select the correct device (5CSXFC6C6U23C8E...
07/21/2014
- Hi,
I'm using the pre-dev MitySOM eval board and I'm trying to rebuild a complete working environment with the cu...
07/20/2014
- Hi,
I originally wanted to connect to the board either usb storage peripherals or webcams-like peripherals. I bou...
07/17/2014
- 05:08 PM Software Development: RE: Pre production (-X) modules with newer sd image
- That update to the conf/local.conf should fix the uImage issue. As for the building of the DTB through yocto, we push...
- 03:42 PM Software Development: RE: Pre production (-X) modules with newer sd image
- Thanks a lot for the feedback.
I have noticed that the Yocto wiki has just been updated concerning the uimage format... - 09:13 AM Software Development: RE: Pre production (-X) modules with newer sd image
- I am currently working through the kit and having a similar experience. The following seems to work for me in regard ...
07/15/2014
- 06:28 PM Software Development: RE: Pre production (-X) modules with newer sd image
- Well, the orange LED switches OFF because with this new version of the SD card, the FPGA is loaded with a firmware at...
07/11/2014
- 09:34 AM Software Development: RE: Building u-Boot and Preloader
- I believe that the files in question need to be copied from software/spl_bsp/generated into u-boot-socfpga/board/cl/m...
07/10/2014
- 02:23 PM Software Development: RE: Breaking changes on early MityARM
- Should have spotted that note but somehow managed to miss it!
Thanks,
Nigel. - 02:00 PM Software Development: RE: Breaking changes on early MityARM
- Hello Nigel,
Sorry about that. The description of the hardware changes for the Dev Kit baseboard are here:
htt... - I have an early MityARM module and dev kit. On trying to implement the latest software versions I found that the Ethe...
- I am just revisiting the development kit after working on other projects and I am trying to locate the copy_files.sh ...
07/08/2014
- Hi,
I'am just starting to discover the eval kit. The one I ordered from Mouser was a pre-prod (- X) version. I und...
07/07/2014
- Hi,
Do you have sample c/c++ program to read/write a memory inside Cyclone V FPGA through hps2fpga bridge interfac...
07/03/2014
- 05:14 PM FPGA Development: RE: How to access FPGA internal memory through AXI slave interface protocol
- Hi Bill,
Sorry for the confusion. The latest image updated the Baud Rate to 115.2kbps to be consistent with the r... - 05:05 PM FPGA Development: RE: How to access FPGA internal memory through AXI slave interface protocol
- Hi,
I downloaded the sd_image_mitysom_5csx_rev1B.zip, and extracted out the .bin file. Then I typed "sudo dd if=sd...
07/02/2014
- 09:27 PM FPGA Development: RE: How to access FPGA internal memory through AXI slave interface protocol
- Information on how to make an SD card based upon the current Development Kit SD card image (Rev 1B) can be found on t...
- 06:17 PM FPGA Development: RE: How to access FPGA internal memory through AXI slave interface protocol
- Mike,
I think you meant "memtool -32 0xFFD0501C=0x06" for brgmodrst register. The reset value of the register some... - 08:52 AM FPGA Development: RE: How to access FPGA internal memory through AXI slave interface protocol
- For reference on the reset register:
http://www.altera.com/literature/hb/cyclone-v/hps.html#reg_default_component/... - 08:51 AM FPGA Development: RE: How to access FPGA internal memory through AXI slave interface protocol
- Hi Bill,
It looks like you are using version 3.8 of the kernel. Version 3.8 does not have the FPGA bridge drivers...
06/27/2014
- 09:52 PM FPGA Development: RE: How to access FPGA internal memory through AXI slave interface protocol
- Hi Mike,
I attached 2 files as you indicated in your previous reply. One is boot.log and another one is foo.txt.
... - 07:56 AM FPGA Development: RE: How to access FPGA internal memory through AXI slave interface protocol
- If you can't see the enable file then the driver for the device isn't compiled in or the device tree blob doesn't ins...
06/26/2014
- 10:46 PM FPGA Development: RE: How to access FPGA internal memory through AXI slave interface protocol
- Thanks for your reply.
I am currently intend to use hps2fpga bridge only in my design. And I just copy the generat... - 08:12 AM FPGA Development: RE: How to access FPGA internal memory through AXI slave interface protocol
- Which AXI crossbar interface are you using? The hps2fpga bridge or the lightweight bridge? Did you make a new prelo...
- Hi,
Could you point to some examples for UART RS232 communication?
Thanks,
Jack
06/25/2014
- Hi,
I have implemented a logic and loaded into cyclone V FPGA. Before that, I did run simulation to access a memor...
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