Mity CPU Platforms » MitySOM-5CSX Altera Cyclone V

08/04/2014

10:06 AM Software Development: RE: Standard USB peripheral connection on MitySOM eval Board

Hello Mr. Bretecher,
We will try to get a procedure posted for this. Sorry for the delay.
-Mike
Michael Williamson

10:05 AM Software Development: RE: Miscellaneous questions

Memtool and the i2c-utils aren't added to our reference filesystem image, but you could add it by modifying the IMAGE... Michael Williamson

09:51 AM Software Development: RE: Performance problem with baremetal code

Hello Mr. Kempter,
We don't normally run / support bare-metal applications here (we find most folks get into more ... Michael Williamson

08/01/2014

11:25 AM Software Development: Performance problem with baremetal code

I tried to do some performance analysis of ARM on MitySOM-5CSX regarding floating point performance in baremetal code... Christian Kempter

07/25/2014

02:42 PM Software Development: RE: PCI-e Device Driver - munmap related error

Can you post your code? Are you getting user space faults and not kernel oops, right?
Are you unmapping with the ... Michael Williamson

01:52 PM Software Development: PCI-e Device Driver - munmap related error

Posting on behalf of a customer:
I'm having some sporadic problems with the device driver I made for our pci-e dev... Alexander Block

07/24/2014

09:05 AM FPGA Development: RE: FPGA DDR3 on 5CSX-H6-42A-RC-X (DDR)

Hi Nigel,
I don't believe there is a way to do it directly in QSYS. You may be able to patch your generated outpu... Adam Dziedzic

07:59 AM FPGA Development: RE: FPGA DDR3 on 5CSX-H6-42A-RC-X (DDR)

Hi Adam,
Thanks for the insights.
Do you know how to persuade qsys to run the DDR at a slower speed? In normal ... Nigel Doe

07/23/2014

04:19 PM FPGA Development: RE: FPGA DDR3 on 5CSX-H6-42A-RC-X (DDR)

Hi Nigel,
You are correct, the C8ES devices do not meet timing with the FPGA DDR according to Quartus. The ES sil... Adam Dziedzic

01:27 PM FPGA Development: FPGA DDR3 on 5CSX-H6-42A-RC-X (DDR)

Although your reference design using FPGA DDR compiles as supplied, when I select the correct device (5CSXFC6C6U23C8E... Nigel Doe

07/21/2014

04:31 PM Software Development: Miscellaneous questions

Hi,
I'm using the pre-dev MitySOM eval board and I'm trying to rebuild a complete working environment with the cu... Pierre-Yves BRETECHER

07/20/2014

09:58 AM Software Development: Standard USB peripheral connection on MitySOM eval Board

Hi,
I originally wanted to connect to the board either usb storage peripherals or webcams-like peripherals. I bou... Pierre-Yves BRETECHER

07/17/2014

05:08 PM Software Development: RE: Pre production (-X) modules with newer sd image

That update to the conf/local.conf should fix the uImage issue. As for the building of the DTB through yocto, we push... Daniel Vincelette

03:42 PM Software Development: RE: Pre production (-X) modules with newer sd image

Thanks a lot for the feedback.
I have noticed that the Yocto wiki has just been updated concerning the uimage format... Pierre-Yves BRETECHER

09:13 AM Software Development: RE: Pre production (-X) modules with newer sd image

I am currently working through the kit and having a similar experience. The following seems to work for me in regard ... Nigel Doe

07/15/2014

06:28 PM Software Development: RE: Pre production (-X) modules with newer sd image

Well, the orange LED switches OFF because with this new version of the SD card, the FPGA is loaded with a firmware at... Pierre-Yves BRETECHER

07/11/2014

09:34 AM Software Development: RE: Building u-Boot and Preloader

I believe that the files in question need to be copied from software/spl_bsp/generated into u-boot-socfpga/board/cl/m... Nigel Doe