Mity CPU Platforms » MitySOM-5CSX Altera Cyclone V

Hello,

If you want to intergate the data inside the FPGA instead of having the HPS involved you could look into using Altera's Triple Speed Ethernet MAC: https://www.intel.com/content/www/us/en/docs/programmable/683402/22-4-21-1-0/example-applications.html. This is a soft MAC core that replaces the MAC in the HPS and allows for your FPGA logic to control the MAC.

Dan

Hi,
I donot have much resources, as my application need more resources, I wanted to use HPS EMAC. And I am not going to implement any other IP layers, I just modify the data part and forward on the other port. For this, I have made emac0 and emac1 of HPS external (by double clicking in platform designer) along with two instances of rgmii splitter conduit signals which are connected to emac0 and emac1 of HPS made external. And these signals in top module connected accordingly, like input signal of HPS emac are assigned with output of rgmii splitter mac signal and vice versa. With this I am getting 60% packet loss in ping, where as if they are connected in platform designer ping is working fine with 0% packet loss. Why so. How can I resolve it. Once this is proved, I wanted to work on txd_o,txen_o,and txer_o signals of rgmii splitter, like modifying the data part of MAC frame and generating the CRC and so on.

Hello,

For the case that you are seeing 60% packet lose, what did you change in the reference FPGA project that was supplied in the bnet_mps project? Also have you verified that your project is meeting timing?

Best regards,
Dan

i had made HPS and emac Splitter Conduit signals to external in Platform Designer and I had assigned that conduit signals properly in top Module accordingly like, hps_0_emac0_phy_txd_o to rgmiib_emac_phy_txd_o and for that reference, please the find the attached screenshots of how i had assigned that signals in top module, with this connections i am facing packet loss in ping operation. What further steps may i take to resolve this packet loss issue. Once this is proved, I wanted to work on txd_o,txen_o,and txer_o signals of rgmii splitter, like modifying the data part of MAC frame and generating the CRC and so on with the data .

It sounds like you are on edge for timing so please verify that your design meets timing via TimeQuest in Quartus. Also when you used the provided reference project you did not see this packet lose, correct?

Dan

Hi,

with the provided reference project there is no packet loss but there are timing errors (screenshots attached) even after modified the reference project, as we said in first query, we observed similar timing errors with the same hold time violation. And this hold time violation is coming from HPS GMII to RGMII Converter intel FPGA IP. How can i Resolve this one?
I
IMG_8677.jpeg
MG_8679.jpeg

Hello,

I have verified that the reference design does meet timing when built via the makefile (ie make rbf). The makefile removes 2 incorrectly autogenerated clock assignments for the MAC clocks. The following lines need to be deleted from dev_5cs/synthesis/submodules/dev_5cs_hps_0_fpga_interfaces.sdc (this files gets generated from Platform Designer):

create_clock -name emac0_tx_clk -period 10.0 [get_keepers {*|fpga_interfaces|peripheral_emac0~internal_clock}] -add
create_clock -name emac1_tx_clk -period 10.0 [get_keepers {*|fpga_interfaces|peripheral_emac1~internal_clock}] -add

Please try to remove those line and see if you timing issue and poor ping performance goes away.

Best regards,
Dan

Hi,

Yeah, I am removed that two lines in dev_5cs/synthesis/submodules/dev_5cs_hps_0_fpga_interfaces.sdc, before updating this one i am getting 30-40% of packet loss in ping , as off now I am updated that one now i am getting 5-7% of packet loss in ping, but i am not getting 0% of packet loss in ping. And also i am observed in my reference FPGA project that was supplied in the bnet_mps project which is we discussed earlier in that project also have that two lines in this dev_5cs/synthesis/submodules/dev_5cs_hps_0_fpga_interfaces.sdc, but with that project i am not facing any packet loss in ping.

Please see the below lines present in my reference FPGA project that was supplied in the bnet_mps project sdc file path of dev_5cs/synthesis/submodules/dev_5cs_hps_0_fpga_interfaces.sdc with this i am not getting 0% packet loss in ping

create_clock -period 10.0 [get_pins -compatibility_mode |fpga_interfaces|clocks_resets|h2f_user0_clk]
create_clock -period 10.0 [get_pins -compatibility_mode *|fpga_interfaces|peripheral_emac0|gmii_mdc_o]
create_clock -name emac0_tx_clk -period 10.0 [get_keepers {|fpga_interfaces|peripheral_emac0~internal_clock}] -add
create_clock -period 10.0 [get_pins -compatibility_mode |fpga_interfaces|peripheral_emac1|gmii_mdc_o]
create_clock -name emac1_tx_clk -period 10.0 [get_keepers {|fpga_interfaces|peripheral_emac1~internal_clock}] -add

Hello,

For the reference project the makefile removes those lines from the sdc file before it does the build, if you aren't using the Makefile for doing the build then you need to manually delete those lines after running Platform Designer generate.

So it sounds like removing the create_clock contraints in dev_5cs_hps_0_fpga_interfaces.sdc helped improve your ping performance but you still are seeing packet lose. Can you please email your quartus project so I can take a look at it (email is dvincelette@criticallink.com). I'm wondering if there still is a timing issue.

Thank you,
dan

Hi,

Actually that timing issues were resolved and ping performance also well as of now without packet loss. And now I am working fine with RGMII splitter connected to the HPS EMAC of latency 2 microseconds in my setup, I want to understand the maximum allowable latency between the RGMII splitter and the HPS EMAC.