Mity CPU Platforms » MitySOM-5CSX Altera Cyclone V

Hi Xiang,

When you enabled the FPGA to HPS SDRAM bridge did you also rebuild your preloader and u-boot? This is needed because the HPS is the one that takes these bridges out of reset.

Best regards,
Dan

Hi Dan,

Thanks for your information, instead of rebuild preload and u-boot, do you have any command that can do release these bridges out of reset? Now, I can use Putty connect system by SSH.

BR,
Xiang

Hi Xiang,

You would need to update the `fpga2sdram_handoff` variable in u-boot to enable the ports that you would like. Here is the HPS doc on the FPGA port controller register map: https://www.intel.com/content/www/us/en/programmable/hps/cyclone-v/hps.html#sfo1411577376106.html

I would still recommend rebuilding the preloader and u-boot because that's normally the foolproof way of enabling the bridge that you want.

Best regards,
Dan

A colleague just informed me that even if you set that variable to enable the bridges, it may still not work because the preloader also enables the bridges as part of configuring the HPS I/Os. Because of this, the correct and supported path is to rebuild and update the preloader and U-Boot with the appropriate bridge settings enabled. This ensures the bridges are released at the correct point in the boot sequence and avoids undefined behavior that can occur if they are manipulated later from user space.

Dan

Thanks Dan, I tried change resigster 0xFFC25080 from 0x00000000 to 0x000003FF, but still timeout. I will update u-boot to try again.