Mity CPU Platforms » MitySBC-Agilex5

Hi! I’ve received a MitySBC-Agilx5 critical link board. Following are the board details:
Model : A5ED-B94-C7F-RC-SBC
Part Number (written on the agilx-5 SOC) : A5ED065BB32AI4S

I bought the dev kit so it came with the complete board setup and pre-booted SD card. The SD card already has an FPGA design (.rbf file) in it named a5e.core.rbf inside the lib/firmware directory of the linux filesystem. I’ve tested the following scenarios:

Scenario 1 : I used the original pre-built board and SD card. The board successfully booted up.

Scenario 2 : Built the example a5e.core.rbf file myself using the guidelines given in the recommended build flow for MitySBC ( [[https://support.criticallink.com/redmine/projects/mitysbc_a5/wiki/Building_fpga_261pro]]). I followed all the steps given in the link for creating the .rbf file and used Quartus 26.1 as mentioned. My board model number was not available in the github repo ( [[https://support.criticallink.com/gitweb/?p=mitysbc-a5-ref.git;a=tree;h=refs/heads/pro_26.1_stable;hb=refs/heads/pro_26.1_stable]] ) i.e., A5ED-B94-C7F-RC-SBC so I used this model number example instead A5ED-B94-C7F-RC-SBC-X from the repo and build the a5e.core.rbf file successfully using the mitysbc-a5e-ref-base example design (https://support.criticallink.com/gitweb/?p=mitysbc-a5-ref.git;a=tree;f=A5ED-B96-C7F-RC-SBC-X/mitysbc-a5e-ref-base;h=a20fd6e7743941e93389af6748492d32e7fd24dc;hb=refs/heads/pro_26.1_stable). I replaced the original a5e.core.rbf file from the pre-loaded SD card with this newly created .rbf file inside lib/firmware directory to test whether this custom .rbf file works or not. I started the board but it gave the following error and didn’t boot up:

U-Boot SMC: Error sending bitstream!
SDM: Config status: (0xf0040000)
SDM Err: Bitstream element not understood. Internal error.
Catchall Error.
Command 'load' failed: Error 4
FPGA not ready. Bridge reset aborted!

Scenario 3 : Instead of just building only the RBF file, I followed the entire recommended build flow guide ( [[https://support.criticallink.com/redmine/projects/mitysbc_a5/wiki#Recommended-Build-Flow:~:text=Pro%20261%2020260809-,Recommended%20Build%20Flow,-%C2%B6]] ), build the following files (used A5ED-B96-C7F-RC-SBC-X model number from the repo):

• a5e.core.rbf
• u-boot.itb
• boot.scr
• mitysom-image-base-mity-a5e.rootfs.tar.gz

And using the above 4 files, I generate the sd_card.img file. I tried to flash this newly created SD card image but got the .rbf file error again:

U-Boot SMC: Error sending bitstream!
SDM: Config status: (0xf0040000)
SDM Err: Bitstream element not understood. Internal error.
Catchall Error.
Command 'load' failed: Error 4
*** FPGA configuration failed, not continuing the boot ***
*** Fix the RBF in /lib/firmware and reset, or boot by hand ***

Scenario 4 : I used my custom created SD card image from scenario 3 and replaced the custom .rbf file with the original a5e.core.rbf file from scenario 1 which was present in the pre-loaded SD card. This one works perfectly fine similar to scenario 1 i.e., my complete custom build with the original a5e.core.rbf file from the pre-loaded original SD card image. This confirmed that the issue is indeed in the custom .rbf file.

Scenario 5 : I created a very small example using Quartus 26.1 using my device part number (A5ED065BB32AI4S). It is a very basic platform design of clk,reset, 1 bit GPIO and generated I its .rbf file successfully. I placed this custom .rbf file in the original pre-build SD card image inside lib/firmware directory but got the same error as scenario 2:

U-Boot SMC: Error sending bitstream!
SDM: Config status: (0xf0040000)
SDM Err: Bitstream element not understood. Internal error.
Catchall Error.
Command 'load' failed: Error 4
FPGA not ready. Bridge reset aborted!

Scenario 6 : I tried the prebuild a5e.core.rbf files available under the files tab on critical link website ( [[https://support.criticallink.com/redmine/projects/mitysbc_a5/files]] ) for Quartus Pro 25.3.1 20260310, Quartus Pro 25.3 20251217, Quartus Pro 24.2 20241119 and A5ED-B96-C7F-RC-SBC-X Quartus Pro 26.1 20260809. Tried all 4 i.e., copied them in the /lib/firmware/ folder of the original SD card image but all 4 of them didn’t work and gave the same error as scenario 2 and 5:

U-Boot SMC: Error sending bitstream!
SDM: Config status: (0xf0040000)
SDM Err: Bitstream element not understood. Internal error.
Catchall Error.
Command 'load' failed: Error 4
FPGA not ready. Bridge reset aborted!

So the main issue is that I’m not able to program the FPGA for my MitySBC board. No matter how basic and small the .rbf file I use, it gives me errors. Can you please provide me with some example build flow for my specific board i.e., A5ED-B94-C7F-RC-SBC as in the github repo no example of this specific board is available or can you please identify my mistake.

Here I've also attached the complete terminal log of the error I received from scenario 2, 5 and 6.