Activity
From 08/20/2010 to 09/18/2010
09/17/2010
- MW 06:32 PM Software Development: RE: LCD/Display questions
- It's off the [[Das_U-Boot_Port]] page from the start page. I'll look at making another entry.
- DV 06:06 PM Software Development: RE: LCD/Display questions
- Could you put the link to that wiki page into the wiki start page please.
- MW 05:52 PM Software Development: RE: LCD/Display questions
- The [[LCD configuration]] wiki page has been started that will cover the information you need. It's a work in progress, but there should be enough info in there now to at least force a frame buffer device into existence for the kernel.
- DO 02:27 PM FPGA Development: RE: How to implement bidirectional BLVDS in the FPGA (Spartan-6 )
- I received a reply back from Xilinx tech support.
They indicated that the approach for Spartan-6 would be similar to Virtex-E devices, and pointed me to an app note covering bidirectional BLVDS.
If anyone is interested, the app note ...
09/16/2010
- DV 08:26 PM Software Development: RE: LCD/Display questions
- I'll need a little more information about the uboot to be able to have it tell the kernel to initialize the device. Are we setting some environment variable here?
- MW 07:01 PM Software Development: RE: LCD/Display questions
- Mr. Schlunk,
The kernel included in the development kit provided should have the necessary code installed to support either the DVI interface or the LCD panel interface. To enable the display, the config options in uBoot must be upda... - We are trying to figure out how to get video out of the board and had a couple of questions.
Does your development kit already come with the settings file for the LCD that you sell, and for the DVI adapter? If not, can you tell me how... - I need to implement a data bus as part of an interface to the Xilinx FPGA, and it must be a bidirectional BLVDS interface. I looked in the Xilinx document: Spartan-6 FPGA SelectIO Resources, v1.3.
On p. 37, there is a diagram that descr...
09/07/2010
- MW 04:12 PM FPGA Development: RE: Critical link bit file
- Actually John,
you shouldn't need to reprogram the NAND/root filesystem. Only the kernel. The NAND should still be OK.
-Mike
- MW 04:10 PM FPGA Development: RE: Critical link bit file
- Right. The procedure you just ran only reloads the bootloader images.
You will also need to reload the kernel image and the root filesystem to boot all the way up.
The binary kernel image (uImage) and the jffs2 image for the roo... - JM 04:03 PM FPGA Development: RE: Critical link bit file
- it gets into uboot but once past uboot I get this
8192 KiB M25P64 at 0:0 is now current device
Wrong Image Format for bootm command
ERROR: can't get kernel image!
- JM 04:01 PM FPGA Development: RE: Critical link bit file
- that worked I am backup and running.
thanks
John - MW 03:52 PM FPGA Development: RE: Critical link bit file
- Hi John,
I copied the instructions wrong from our factory programming instruations. Sorry. The "-c" option should have been a "-v" option.
The command should have read: - JM 03:43 PM FPGA Development: RE: Critical link bit file
- I ran this exactly how you said and I get the usage for the command here is what I typed in
sfh_OMAP-L138 -flash -c -p COM1 UBL_SPI_MEM.ais u-boot.bin
John - MW 01:38 PM FPGA Development: RE: Critical link bit file
- Look at the [[Reprogramming a Dead Board]] wiki link. Let me know if you run into trouble.
-Mike
- JM 01:18 PM FPGA Development: RE: Critical link bit file
- It was my fault not yours so no big deal. If you can post what it takes to re-flash the boot code. If this doesn't work I can ship it back to you.
I will make sure to type in verbatim what you show.
thanks
John - MW 07:54 AM FPGA Development: RE: Critical link bit file
- Hi John,
Well, the bad news is that I think you whacked the bootloading code on the SPI FLASH.
The "sf write" command was expecting, I think, a hex arguement for the filesize, and you passed it the decimal equivalent. This told it... - MW 07:57 AM Software Development: RE: Audio help needed
- Hi Otmar,
The API will be ALSA.
My best guess would be something mid-October. We'll try to bump it up on the priority list here.
-Mike
09/03/2010
- JM 06:40 PM FPGA Development: RE: Critical link bit file
- Nothing at all unless I hit both buttons and then I see BOOTME.
here is the console after doing the Kermit upload
U-Boot > loadb 0xc07000000
## Ready for binary (kermit) download to 0x07000000 at 115200 bps...
## Total Size ... - MW 06:35 PM FPGA Development: RE: Critical link bit file
- Do you have a text capture of the commands you typed?
You need to be careful executing commands that write to the NOR, you can correupt the bootloader code....
When you power cycle, do you see anything out of the serial port at all... - JM 06:32 PM FPGA Development: RE: Critical link bit file
OK I went through all of that and now my platform does not boot at all. no text coming across on the serial port.
John- MW 04:14 PM FPGA Development: RE: Critical link bit file
- Sorry, tftp is network transfer protocol. Didn't know you weren't on the network.
If you would like to transfer the data using a serial port, you should be able to a kermit transfer. To load the file via serial type:
loadb 0xC070... - JM 03:47 PM FPGA Development: RE: Critical link bit file
- Why would I have q network cable plugged in and what to I plug it into? My home network? I am using the serial port to connect to the development station.
If I plug it to my home network how to I specify where the file is?
John - MW 03:38 PM FPGA Development: RE: Critical link bit file
- This usually means that the network cable isn't plugged in or the other end isn't talking.
- JM 03:09 PM FPGA Development: RE: Critical link bit file
- When trying to load the FPGA through Uboot I get this error
T WARN: emac_send_packet: No link
T WARN: emac_send_packet: No link
T WARN: emac_send_packet: No link
T WARN: emac_send_packet: No link
T WARN: emac_send_packet: No lin... - JM 02:57 PM FPGA Development: RE: Critical link bit file
- It looks like it works once I tri-stated the wait signals I can not reproduce the problem.
I sent a new file to our software guys to confirm they do not see a problem but I am confident the problem is fixed.
thanks for you help
... - JM 01:22 PM FPGA Development: RE: Critical link bit file
- We only use CS2 and the IO_EMA_D bus is only driven when CS2 and OE are active.
I have the wait signals driven high so this may be the issue I am going to float them and retry thanks. If this doesn't work I will do the other reco... - MW 11:26 AM FPGA Development: RE: Critical link bit file
- Also, if you'd like to send me your project file (offline, if you'd prefer) we could arrange that. Then we can at least review it or try it here.
- MW 11:24 AM FPGA Development: RE: Critical link bit file
- John. Quick question: which chip select space are you using to talk to the FPGA? We have wired all of them over to the FPGA. CS3 is reserved for the NAND interface. Please ensure that CS3, the EMA_D, and EMA_WAIT0 lines are tristate...
- Can you send me the bin and bit file for your FPGA. I am trying to debug the crash that happens when we program our FPGA. I think I have reproduced it on my system and I have confirmed it does no happens If I do not program the FPGA....
08/31/2010
- OS 07:06 PM Software Development: RE: Audio help needed
- Hi Mike,
Thank you for the information.
Once the drivers exist -- would you know what API I should probably be using -- e.g. ALSA or OSS or just fopening the device?
Also, so we can plan things a bit better on our end, is there... - MW 05:20 PM Software Development: RE: Audio help needed
- Hello Mr. Schlunk,
Unfortunately, in order to use the audio output a new sound "board/driver" needs to be written and added to the kernel/sound/soc/davinci section of the linux kernel for the Industrial I/O board. We have started on... - JM 04:08 PM FPGA Development: RE: FPGA Unused Pins
- Thanks
- MW 03:47 PM FPGA Development: RE: FPGA Unused Pins
- Hi John,
In general, you should tri-state / float all unused pins on the FPGA. This will result in those pins behaving the same as when the FPGA is not programmed (e.g., during power up, etc.). Any pins connected between the FPGA an... - Did you have to do anything special to the unused EMIFA pins like
I_EMA_CS0_N
I_EMA_CS3_N
I_EMA_CS5_N
I_EMA_CAS
I_EMA_RAS
I_EMA_SDCKE
I_EMA_RNW
to insure that the FPGA does not interfere with the EMIFA bus?
I have lo... - JM 04:05 PM FPGA Development: RE: Digital DNA
- Yes but I think the range of the DNA value is assigned per customer so each customer has a unique set of values and no other companies can buy the FPGA with those values. At least this is how the Xilinx FAE explained it to me, this wil...
- MW 03:53 PM FPGA Development: RE: Digital DNA
- Stuff you probably already know, but:
According to our distributor, the Xilinx DNA code is unique per chip (like a serial number) and you cannot request codes, they are assigned and burned in at factory. You can access them using the...
08/30/2010
- I'm trying to figure out a simple method of getting a sound file to play on the board from our app.
After looking around a bit, I'm still not sure what I should be doing. Can anyone point me in the right direction?
- JM 02:36 PM FPGA Development: RE: Accessing the FPGA Memory space using U-boot
- Hey I figured it out so never mind. the FPGA is at 0x6000000 and the memory commands in Uboot seem to work.
- I sent this messge to our software guys also but if youcan help it would be appreciated.
In order to debug the FPGA I need the ability to read and write memory locations. I need some help to get this working on my development stat... - JM 01:37 PM FPGA Development: RE: Digital DNA
- We do no need it on the MityDSP board I was just curious. We are using it on our PROBE FPGA. If you had one assigned it would give us the ability to verify it and confirm that the FPGA is a Critical Link FPGA, another level of security...
08/27/2010
- MW 03:37 PM FPGA Development: RE: Digital DNA
- Hi John,
We're still looking into this here (I wanted to at least get you some feedback that someone saw your post). The immediate answer is, "no we haven't specifically requested a DNA value be assigned".
We haven't used the Digi...
08/26/2010
- Did you get a digital DNA value assigned for your FPGA's?
08/24/2010
- TC 09:11 PM FPGA Development: RE: POWER DOWN Memory Corruption
If your application will not be writing to the NAND flash then you should not need hold-up circuit from the motherboard. However, if you plan to mount a user filesystem rw, and plan to write to it during normal operation, then you may ...- JM 09:04 PM FPGA Development: RE: POWER DOWN Memory Corruption
- So do you think we need to put on our mother board a circuit to hold up the power and interrupt the OMAP to let it know power is going down? Or do you think that your read-only mount will be all that is needed?
thanks for the quick r... - TC 08:58 PM FPGA Development: RE: POWER DOWN Memory Corruption
- John -
We are indeed aware of this and are working on a solution. We plan to allow for the root file system to be mounted as a read-only file system (currently it's mounted read-write). Mounting the root file system read only will al... - Software guys tell me they had a case where the FLASH memory was corrupted when the power was removed at the wrong time. This would be a disaster for us if this happened in the operating room. It sounds like we need to have either a...
- MP 06:51 PM FPGA Development: RE: Programming the FPGA
Hi John.
It looks like you are generating the .BIN file using the bitgen tool ("Generate Programming File" step in ISE), instead of the required iMPACT tool method. While the bitgen tool does in fact generate a .BIN file, it doesn'...- JM 04:00 PM FPGA Development: RE: Programming the FPGA
- Here is the .BGN but there were no .CFI or .PRM files in the FPGA directory.
- MP 03:44 PM FPGA Development: RE: Programming the FPGA
Hi John.
Would you be able to upload the .BGN .CFI & .PRM files that go with the .BIN file you have already uploaded? These are report files that get generated with the .BIT and .BIN files. I suspect there is a problem with a sett...- We are using the MityDSP-L138. Our software guys are not able to program my FPGA bin file using your routine. Your routine only programs the bin file that you provided and does not seem to light the green LED for the BIN file I provide...
08/23/2010
- JP 02:34 PM Software Development: RE: Rescanning the Nand flash
- Dennis,
Just so you know, the suggestions below are not based on personal experience.
Not sure there is a command to do exactly what you are looking for. There is the "nand scrub" command and it comes with a warning:
Warning: sc... - I made a type-o when loading the Nand flash. I managed to convince the flash that it has a whole bunch of bad areas. Is there a utility to tell the system to "delete" all bad areas and rescan the flash to see which are really bad?