Activity
From 03/07/2013 to 04/05/2013
04/04/2013
- 04:27 PM Software Development: RE: L138 - DSP Timer interrupt question ...
- Mike,
Can you add more details regarding this statement: _The DSP loop optimization can create large interrupt lat... - 11:43 AM Software Development: RE: MityDSP-L138F Failure to Boot and Cannot Reset
- Also feel free to look through the wiki http://support.criticallink.com/redmine/projects/arm9-platforms/wiki
- 11:40 AM Software Development: RE: MityDSP-L138F Failure to Boot and Cannot Reset
- The username for the modules should be _root_
04/03/2013
- 10:16 PM Software Development: RE: MityDSP-L138F Failure to Boot and Cannot Reset
- Hi,
Thank you so much for supporting.
For (1): At the first time. Now the board are running with null modem cable... - 07:17 AM Software Development: RE: MityDSP-L138F Failure to Boot and Cannot Reset
- I am assuming these are out of the box Development kits?
For (1) the console UART, please ensure you are using the... - 08:27 AM PCB Development: RE: Resistors in EMA signal and adress traces?
- Mike,
it's the L138-FX-225-RC Module. No FPGA.
I'm concerned about both kinds of traces.
Christian - 07:33 AM PCB Development: RE: Resistors in EMA signal and adress traces?
- Which part number? Specifically, does the module include an FPGA or not?
Which EMA traces are you concerned with,... - Hi,
can anybody tell me if there are already resistors on the EMA-traces on the L138-Modul integrated? If yes, wha...
04/02/2013
- Hello
I am using Industrial I/O board(80-000268RI-2 A) and 2 L138 board (L138-CG-225-RC ,L138-FG-225-RC).I got 2 i...
03/28/2013
- Trying to install an intel 330 series SSD (60 Gb). I have a power brick for it and plugged that in. Connected to th...
03/26/2013
- 11:48 AM Software Development: RE: SPI NOR Flash memory map
- You are correct, Mike. The flash does have to be erased before writing. Here is a more fleshed out version of my cod...
- 11:13 AM Software Development: RE: SPI NOR Flash memory map
- BTW:
It's not entirely clear to me if the write routine above will work properly. I don't know for sure, off-hand... - 11:11 AM Software Development: RE: SPI NOR Flash memory map
- The SPI partitions are defaulted in the board-mityomapl138.c file in arch/arm/mach-davinci in the spi_flash_partition...
- 10:55 AM Software Development: RE: SPI NOR Flash memory map
- Please allow me to chime in with a similar question... I have "reorganized" the upper part of the spi nor flash on my...
03/22/2013
- 03:13 PM Software Development: RE: Creating a Read-Only Filesystem
- I worked on it some more and ended up with a script with seven patch files that change it to a read-only filesystem. ...
- 01:01 PM FPGA Development: RE: L138F - FPGA gets incorrect data from UPP
- Marek,
The UPP clocks may be sourced by either the FPGA or the OMAP-L138 based on your configuration requirements.... - Hello,
I have problem when trying to read data on UPP by FPGA (sent from OMAP - working with L138F, XC6SLX45, ISE ...
03/20/2013
- 09:16 AM Software Development: RE: Creating a Read-Only Filesystem
- Jim,
Any luck? As far as I can tell that mount entry should work.
03/15/2013
- 11:32 AM Software Development: RE: MDK_2012-08-10 default configuration
- Mike,
Thanks for pointing that out - really helpful!
I can most definitely see the network (and boot from it) from ...
03/14/2013
- 08:25 PM Software Development: RE: MDK_2012-08-10 default configuration
- So the industrial IO board uses PHY address 3 and the EMAC driver is configured to look for that MDIO interface prior...
- 07:06 PM Software Development: RE: MDK_2012-08-10 default configuration
- My custom board uses either PHY address 1 or 0 - both addresses cause the same problem.
I played around a little wit... - 08:59 AM Software Development: RE: Creating a Read-Only Filesystem
- I changed fstab for the /mnt/user_nand to as follows -
/dev/mtdblock1 /mnt/user_nand jffs2 defaults...
03/13/2013
- 04:06 PM Software Development: RE: Creating a Read-Only Filesystem
- > rm: cannot remove '/etc/volatile.cache': Read-only file system
> chown: /var/volatile/cache: Read-only file system... - 03:56 PM Software Development: RE: Creating a Read-Only Filesystem
- Your fstab entry doesn't have auto in the options list so it isn't auto mounted on startup. You should probably use ...
- 01:20 PM Software Development: RE: SPI NOR Flash memory map
- This probably doesn't completely answer your question, but may be helpful. There is some "spare" memory on the SPI NO...
- 10:59 AM Software Development: RE: MDK_2012-08-10 default configuration
- What PHY address does your custom baseboard use?
-Mike
- Hi,
I am working on bringing up a custom base board for a MityDSP-L138.
Most things seem to work fine using the ve...
03/12/2013
- 02:59 PM Software Development: RE: FPGA Memory Size
- You are correct we are looking at cs5 as well.
32k would probably be sufficient. We typically prefer to provide th... - 01:52 PM Software Development: RE: Creating a Read-Only Filesystem
- I had used -
mount -t jffs2 /dev/mtdblock1 /mnt/user_nand
and just -
mount /mnt/user_nand
also works.
- 01:42 PM Software Development: RE: Creating a Read-Only Filesystem
- "I can manually mount /mnt/user_nand and access that partition"
Whats the full command you use to manually mount you... - Hi,
We use the MityDSP-L138 in a factory automation product and need to prevent fs corruption from random shutdowns.... - 08:32 AM Software Development: RE: SPI NOR Flash memory map
- This appears to be what your looking for.
[[MityDSP-L138_Architecture]]
Also can be determined by looking at the ... - (posted for a customer)
We are looking at using the SPI flash and/or NOR flash for storing our software on the L13...
03/11/2013
- 07:58 PM Software Development: RE: FPGA Memory Size
- As mentioned on the "EMIFA wiki page":http://support.criticallink.com/redmine/projects/arm9-platforms/wiki/EMIF_Inter...
- The standard FPGA memory available to the arm processor within angstrom is currently limited to 2k.
From what we c... - 12:49 PM FPGA Development: RE: SPI Core on FPGA: Implementation on MityDSP-L138F
- Dear all,
I'm trying to understand the behaviour of your SPI core on FPGA with hooked FIFO and wondering how to conn...
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