Mity CPU Platforms

11/25/2014

07:46 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Writing to HPS memory

I would recommend contacting your Arrow FAE or Altera for help with the device tree generation / sopcinfo file.
Yo... Michael Williamson

07:39 AM MitySOM-5CSX Altera Cyclone V FPGA Development: Writing to HPS memory

Hi,
I'm want to use the hps_ddr_write_example design from critical link and test it on Arrow Terasic Cyclone V SOC... Vidya Govindan

11/24/2014

09:23 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: inotify issue

This is a non-problem. It is working fine. Sorry for the trouble. Chris Coonan

09:12 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: inotify issue

Could you provide some example code that shows the problem you are having? Also need a better explanation of what pro... Jonathan Cormier

07:31 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: inotify issue

My mistake. Cut and paste error. The kernel is 2.6.34-RC1.
Chris Coonan

11/22/2014

12:09 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: inotify issue

Trying to get inotify to execute properly from inside my application code. I am using linux kernel 2.24-RC1.
Are t... Chris Coonan

11/17/2014

05:16 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: FPGA configuration via u-Boot problem

You can also use the promgen command to generate a bin file from a bit:
promgen -w -p bin -u 0 filename.bit -o fil... Gregory Gluszek

02:35 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Kernel Driver

Hi
I compiled the kernel driver with the Linux kernel in the instruction here (https://support.criticallink.com/re... Anonymous

07:29 AM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: PlanAhead issue

For ISE (and I think ISE / PlanAhead are still the tools for Spartan 6, as the Vivado tools are for 7 series and high... Michael Williamson

03:21 AM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: PlanAhead issue

Hi,
Why at creation of the project in PlanAhead 14.7 for the chip xc6slx45csg324-3 it is not possible to specify Tem... Oleh Mela

11/14/2014

07:51 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: FPGA configuration via u-Boot problem

Hey,
I solved the problem.
It's important that the FPGA config file <fpga>.bin file was created correctly.
By... Stefan Krassin

07:30 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: FPGA configuration via u-Boot problem

Hi all,
I have a problem with the configuration of the FPGA and booting linux.
I followed the instructions from... Stefan Krassin

11/13/2014

04:26 PM MitySOM-5CSX Altera Cyclone V Software Development: Kernel Driver

Hi,
I'm trying to lad a kernel driver by following example on this page https://github.com/zhemao/interrupt_exampl... Anonymous

11/12/2014

02:38 PM MitySOM-5CSX Altera Cyclone V Software Development: SOCKIT GSRD

Hi,
For my project, I'm trying to use precompiled Linux libraries with Sockit as seen in this link "http://rocketb... Anonymous

11/10/2014

01:52 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Real time SATA writes

Hi Mary,
As you suspected in your original post, it is likely that when you are calling fwrite, in some cases the ... Dominic Giambo

01:04 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Real time SATA writes

After further testing and setting optimization, I have narrowed down the delay:
The call to fwrite() normally take... Mary Frantz

11/07/2014

02:22 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Modular SGDMA

Hi Jack,
We don't have any explicit examples of this but you will want to look into the userspace I/O driver. This... Daniel Vincelette

11/05/2014

01:40 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Modular SGDMA

Hi Dan,
The issue seems to be with the polling. I brought out the empty signal to an oscilloscope and found that i... Anonymous

10/31/2014

10:44 AM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: Clock for FPGA

Hi.
I'm using MityDSP-L138F Board. As will ensure that the generated clock signal to FPGA?
Thanks Oleh Mela

10/29/2014

10:58 AM MitySOM-5CSX Altera Cyclone V Software Development: RE: Performance problem with baremetal code

In the meanwhile and after an ARM Cortex training I've found the root cause of the problem:
For enabling the cache... Christian Kempter

10/28/2014

11:48 AM MitySOM-335x (ARM Cortex-A8 Based Products) PCB Development: RE: RTC Crystal Specifications

Theres a 24MHz crystal between XTALOUT and XTALIN on the ARM. Its frequency tolerance at 25C is +/- 25ppm.
Note th... Jonathan Cormier

11:42 AM MitySOM-335x (ARM Cortex-A8 Based Products) PCB Development: RE: RTC Crystal Specifications

Great, thank you for the information. Is it a similar specification for the other oscillator on the board, connected ... Chris Leon

11:31 AM MitySOM-335x (ARM Cortex-A8 Based Products) PCB Development: RE: RTC Crystal Specifications

For the 32khz crystal attached between the OSC32KOUT and OSC32KIN pins, according to its datasheet, the frequency tol... Jonathan Cormier

10:56 AM MitySOM-335x (ARM Cortex-A8 Based Products) PCB Development: RTC Crystal Specifications

What are the ppm drift specifications for the TPS65910 RTC crystal? Chris Leon

10/27/2014

04:10 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: Communicating with an 8-bit parallel interface (GPIO, SPI or GPMC)

Updated question(s) from the customer:
I've been looking into using GPMC. The Technical Reference Manual for the A... Alexander Block