Mity CPU Platforms

07/18/2019

06:00 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Change data between ARM(Linux) - DSP (bare-metal)

Hi, thanks for reply!
Two follow up questions:
Concerning "you may want to look at some of the DSPlink or syslink c... Aviv Prital

07/17/2019

03:04 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Change data between ARM(Linux) - DSP (bare-metal)

Note if your writing your own bare-metal communication you may want to look at some of the DSPlink or syslink code as... Jonathan Cormier

02:05 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Change data between ARM(Linux) - DSP (bare-metal)

Thanks for the prompt reply!
I'm thinking about shared RAM that ARM user space linux driver will be able to mmap in ... Aviv Prital

02:01 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Change data between ARM(Linux) - DSP (bare-metal)

Could you provide more information on what is suitable for your project? Jonathan Cormier

01:44 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: Change data between ARM(Linux) - DSP (bare-metal)

Hi,
I'd like to use MityDSPL138 kit in order to develop ARM(Linux) - DSP (bare-metal) data exchange over shared memo... Aviv Prital

07/08/2019

02:57 PM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: Reference Project AnalogExpansionSuite query

Hi,
I have a custom board with
-- MityDspl-138F module (with FPGA)
-- No Ethernet port
-- UART,USB,SD CARD int... Vivek Ponnani

10:05 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uPP receive clock lower limitation in SDR (Single Data Rate mode)

Thanks Greg for your reply and sorry for the late reply.
I will forward your response to our FPGA team. They are u... Vivek Ponnani

07/03/2019

11:04 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Set timing constraints

Hi Davide,
You really need a constraints file for this to constrain the input timing signals properly based on the... Michael Williamson

09:20 AM MitySOM-5CSX Altera Cyclone V FPGA Development: Set timing constraints

Dear all,
I have a MitySOM 5CSX-H6-4YA with a Cyclone V SoC installed on a custom board with ADCs and DACs. What I... Davide Vaccaro

07/01/2019

11:03 AM MitySOM-5CSX Altera Cyclone V Software Development: RE: FPGA PIO interrupt issues with Rocko and kernel 4.9

Hi Wesley
Thank you for the proposed code change, that did the trick!
I think @static DRIVER_ATTR(fpga_uinput, S_IR... V J

06/28/2019

03:53 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: FPGA PIO interrupt issues with Rocko and kernel 4.9

Thanks for the log and module code.
We'd like to build this module in an attempt to recreate the issue, but the de... Wesley Dahar

10:04 AM MitySOM-5CSX Altera Cyclone V Software Development: RE: FPGA PIO interrupt issues with Rocko and kernel 4.9

Hi Dan, thanks for your reply.
I did a quick test where I replaced the 4.9 (RT) zImage with 4.1.22(RT) on my rocko... V J

06/27/2019

08:21 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: FPGA PIO interrupt issues with Rocko and kernel 4.9

Hello,
We aren't aware of any changes or issues with the PIO interrupts. We haven't been able to recreate the issu... Daniel Vincelette

12:42 PM MitySOM-5CSX Altera Cyclone V Software Development: FPGA PIO interrupt issues with Rocko and kernel 4.9

Hi
After upgrading to Rocko and kernel 4.9 (RT) my pio interrupt routine is no longer working. My previous setup was... V J

06/26/2019

08:13 AM MitySOM-5CSX Altera Cyclone V Software Development: cannot boot a kernel with kexec

I use MitySOM-5CSX dev kit and i would like to boot to a different kernel using kexec.
In my configuration:
... aggelis aggelis

06/24/2019

04:38 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uPP receive clock lower limitation in SDR (Single Data Rate mode)

Hi Vivek,
I believe the datasheet is saying that regardless of whether the clock is being used as DDR or SDR the ... Gregory Gluszek