Activity

From 07/16/2024 to 08/14/2024

01:48 AM MitySOM-C10GX Hardware Design: RE: JTAG Interface: Hello,
Regarding the first question, unfortunately, the 2.5 V levels being used for the Max10 FPGA will not be co... Gregory Gluszek

09:24 PM MitySOM-C10GX Hardware Design: JTAG Interface: (Posted on behalf of a customer)
On my existing system, the Max10 FPGA has the USB Blaster interface that uses 2... Thomas Catalino

12:52 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: MitySOM-5csx custom board PL fabric ethernet access: Hi,
Actually that timing issues were resolved and ping performance also well as of now without packet loss. And no... Bhardwaj Kotha

03:39 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Receive and send data using vlan tag: Bhardwaj
There should be no devicetree changes necessary to use the VLAN feature of the Ethernet.
You verified that... Tim Iskander
05:55 AM MitySOM-5CSX Altera Cyclone V Software Development: Receive and send data using vlan tag: Hi,
I am working on ethernet using vlan. I had used the ip command to create the vlan after that some data sent f... Bhardwaj Kotha

05:36 PM MityDSP-L138 (ARM9 Based Platforms) PCB Development: RE: X1 component SiLabs 590 BA100M000G depopped: See "PCN20220621000":https://support.criticallink.com/redmine/attachments/download/31707/PCN20220621000.pdf linked fr... Jonathan Cormier
02:09 PM MityDSP-L138 (ARM9 Based Platforms) PCB Development: X1 component SiLabs 590 BA100M000G depopped: Hello,
we are working on transferring our design from the Spartan 6 build to the A7 SOM and an engineer noticed n... Rachel Shaska

07:47 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: how to access gpio using pio ip core in c code: Hello,
I would look at the avalon memory mapped slave address in your signal tap. It's possible the hps is reques... Gregory Gluszek

02:31 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Serial port 2 issue, RS485, RTS drops to early: I figure it's about 10% of the CPU when operating 1200 baud and 1 response per second; it gets much lower as you appr... Fred Weiser
07:11 AM MitySOM-5CSX Altera Cyclone V Software Development: RE: how to access gpio using pio ip core in c code: Hi,
Yes, I am verified in Signal Tap only. and as off now like, we are able to do read and write HPS to FPGA using... Bhardwaj Kotha

04:12 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: how to access gpio using pio ip core in c code: It looks like you posted a couple different versions of your C code. Which one are you running and what does the outp... Gregory Gluszek

07:21 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Serial port 2 issue, RS485, RTS drops to early: > before shutting off the 485 driver
Any idea how often the shutting down occurs? Jonathan Cormier
07:19 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Serial port 2 issue, RS485, RTS drops to early: I patched the 8250.c file to increase the 10ms timeout. I found the timeout is really there only to assure the uart t... Fred Weiser
03:16 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: how to access gpio using pio ip core in c code: Hi,
In my implementation, the Avalon Memory Mapped interface automatically assigned a base address in platform des... Bhardwaj Kotha

06:14 PM MityDSP-L138 (ARM9 Based Platforms) PCB Development: RE: MityDSP-L138F Block Diagram Inconsistencies: Dan,
That clears things up perfectly. Thank you for a quick and comprehensive response. Dylan Louviaux
06:10 PM MityDSP-L138 (ARM9 Based Platforms) PCB Development: RE: MityDSP-L138F Block Diagram Inconsistencies: Hi Dylan,
The external input to the Boot Config Block is the EXT_BOOT# signal pin bin 12 of the SO-DIMM connector.... Daniel Vincelette
04:06 PM MityDSP-L138 (ARM9 Based Platforms) PCB Development: MityDSP-L138F Block Diagram Inconsistencies: All,
I am designing a carrier board for the MityDSP-L138F with A7 FPGA. I have noticed some inconsistencies with the... Dylan Louviaux
02:11 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: MitySOM-5csx custom board PL fabric ethernet access: Hello,
For the reference project the makefile removes those lines from the sdc file before it does the build, if y... Daniel Vincelette
06:45 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: MitySOM-5csx custom board PL fabric ethernet access: Hi,
Yeah, I am removed that two lines in dev_5cs/synthesis/submodules/dev_5cs_hps_0_fpga_interfaces.sdc, before u... Bhardwaj Kotha

07:40 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: MitySOM-5csx custom board PL fabric ethernet access: Hello,
I have verified that the reference design does meet timing when built via the makefile (ie make rbf). The m... Daniel Vincelette

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