Mity CPU Platforms

02/12/2026

03:19 PM MitySBC-Agilex5 Software Development: RE: Eclipse Application

Thank you this is very helpful, What is the best was to debug that you recommend? Brady Heater

02/11/2026

10:31 PM MitySBC-Agilex5 FPGA Development: RE: 25.3 projects can't get recompiled

Eleonora,
If you are asking what clock to drive your IOPLL clock with, you should be able to use the same clock FP... Mike Fiorenza

10:24 PM MitySBC-Agilex5 FPGA Development: RE: 25.3 projects can't get recompiled

Eleonora,
Glad to hear you were able to build the projects!
HPS_CLK_25MHz is a 25 MHz oscillator for the HPS (C... Mike Fiorenza

10:12 PM MitySBC-Agilex5 FPGA Development: RE: 25.3 projects can't get recompiled

Thank you, Mike, for your reply.
The problem really was the Windows inability to works with long paths. I was able ... Eleonora Haralanova

09:10 PM MitySBC-Agilex5 FPGA Development: RE: 25.3 projects can't get recompiled

Hi Eleonora,
Are you using Quartus Pro 25.3 version exactly? If so, do you also happen to be on Windows and this r... Mike Fiorenza

06:46 PM MitySBC-Agilex5 FPGA Development: 25.3 projects can't get recompiled

Hello,
I'm trying to recompile any of the design for 25.3 and even after installing the patch for Quartus Pro, I get... Eleonora Haralanova

01:15 AM MitySOM-C10GX Firmware: RE: Clock EN signal and I2C Dual purpose pin

Hello Mike,
Thanks for the quick response and confirmation of the updated
documentation.  We are working on impl... Dean Rasmussen

12:33 AM MitySOM-C10GX Firmware: RE: Clock EN signal and I2C Dual purpose pin

Dean,
Sorry for the confusion! I see that was incorrect in the previous version of the datasheet now that I've che... Mike Fiorenza

02/10/2026

11:55 PM MitySOM-C10GX Firmware: RE: Clock EN signal and I2C Dual purpose pin

Oh, I have an old version of the datasheet (August 8 2024) that says this. Grabbing the updated version now from your... Dean Rasmussen

11:09 PM MitySOM-C10GX Firmware: RE: Clock EN signal and I2C Dual purpose pin

Hi Dean,
Pin AH2 is our CLKUSR enable pin. This does not leave the SOM and only goes to the enable pin of the 100 ... Mike Fiorenza

10:49 PM MitySOM-C10GX Firmware: Clock EN signal and I2C Dual purpose pin

Regarding FPGA ball location AH2 "SCL_1V8". From my understanding, this pin can be driven low to enable the 100MHz CL... Dean Rasmussen

02/09/2026

08:14 PM MitySBC-Agilex5 Software Development: RE: Eclipse Application

Hi Brady,
In order to build an ARM application for the Agilex 5 on your PC you first need to obtain a toolchain so... Mike Fiorenza

07:16 PM MitySBC-Agilex5 Software Development: Eclipse Application

What is the best was to set up an environment preferable eclipse to build an application. Brady Heater

03:49 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout

Hi Dan,

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please see attached picture, that's a typo when I fill this page.
... Xiang Shuai

02/06/2026

10:17 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout

Hi Xiang,
It looks like you have spelling mistake in your command, it should be the following:... Daniel Vincelette

09:11 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout

Hi Dan,
I meet an issue at step 4 configure and build U-boot and the SPL.
$ make socfpga_nitysom5cs_defc... Xiang Shuai

02/05/2026

09:42 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout

Hi Xiang,
The fpga2sdram_handoff vairable will be set from the quartus project so you don't need to manually chang... Daniel Vincelette

09:04 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout

Hi Dan,
I download uboot-socfpga.tar.gz, but I don't know how to update `fpga2sdram_handoff` variable in u-boot... Xiang Shuai

02/03/2026

04:42 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout

Thanks Dan, I tried change resigster 0xFFC25080 from 0x00000000 to 0x000003FF, but still timeout. I will update u-boo... Xiang Shuai

04:11 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout

A colleague just informed me that even if you set that variable to enable the bridges, it may still not work because ... Daniel Vincelette

03:58 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout

Hi Xiang,
You would need to update the `fpga2sdram_handoff` variable in u-boot to enable the ports that you would ... Daniel Vincelette

02:36 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout

Hi Dan,
Thanks for your information, instead of rebuild preload and u-boot, do you have any command that can ... Xiang Shuai

02/02/2026

09:59 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout

Hi Xiang,
When you enabled the FPGA to HPS SDRAM bridge did you also rebuild your preloader and u-boot? This is ne... Daniel Vincelette

09:28 PM MitySOM-5CSX Altera Cyclone V FPGA Development: JTAG_avalon_master access HPS DDR timeout

Hi,
Using MitySOM_5CSX, I added FPGA to HPS SDRAM interface avalon-mm read-only, and try to using jtag_avalon_... Xiang Shuai