Activity
From 09/25/2011 to 10/24/2011
10/24/2011
- GG 04:06 PM Software Development: RE: RS-485 failure to operate
- Hi Mark,
My initial inclination would be to make sure that the pinmux is set correctly. Section 11.5.10 in the OMAP-L138 Reference Guide has more details on this if you haven't already verified these settings.
Are you trying to com... - Using a MityDSP L178 with industrial IO board 80-000268RI-2
Trying to use RS-485 via J504 - there are no signs of life on any of the pins - even tried manipulating the GPIOs directly. Any ideas?
Note: We were able to toggle other G...
10/21/2011
- SW 02:34 PM Software Development: RE: uPP receive problem
- Mike,
I will attach the upp control settings and dma descriptor settings. I know in the end I want to use the enable on the receive channel. I had disabled that in testing just to see if any data was clocked in. What worries me is ...
10/20/2011
- MW 05:47 PM Software Development: RE: uPP receive problem
- On the MityDSP-L138F, the voltage domain for the UPP (and for the FPGA bank connected to the UPP) is 1.8 Volts.
I'm not entirely sure, on receive, you want to disable the start and enable lines. It might be useful to post your UPP re... - SW 04:56 PM Software Development: RE: uPP receive problem
- Tom,
I understand the handshaking can be a problem. I have the uPP running with the highest divisor now at ~4.68 MHz xmit clock. My concern is that I have disabled the start and enable on the receive channel. With those disabled I ... - TC 01:23 PM Software Development: RE: uPP receive problem
- Hi Scott -
Thanks for posting.
I talked to the guys about this problem that you're having. It sounds like any number of issues in the handshake between the FPGA and the uPP peripheral could be causing your issue. They mentioned D... - Hello,
I am writing a linux uPP driver for bi-directional comms between the fpga and OMAP. From what I can tell the FPGA is receiving data from the OMAP correctly, but THe OMAP is not getting the return data from the FPGA. In our cur... - RB 03:11 PM Software Development: RE: Using dspQDMA library on OMAP-L138
- Great! Thanks very much guys. This should get me on the right track.
- DR 12:41 PM Software Development: RE: Using dspQDMA library on OMAP-L138
- Mike and I apparently were typing simultaneously! Good thing we both came up with the same answer!
Dave
- DR 12:40 PM Software Development: RE: Using dspQDMA library on OMAP-L138
- Typically, we kick off the DMA from an ISR and pend for it in a task. Pending from within an ISR is not allowed. You could kick off the DMA from with the timer function, and pend for the semaphore within a monitoring task. This will av...
- MW 12:35 PM Software Development: RE: Using dspQDMA library on OMAP-L138
- If you are calling SEM_pend() from within an ISR, you need to use a zero timeout. You could do a
- RB 12:16 PM Software Development: RE: Using dspQDMA library on OMAP-L138
- If I did want to be sure that the operation had completed before moving on, is there an alternative approach. In this case polling would probably be ok, but I didn't see any methods in the class to support polling.
-rb - RB 12:15 PM Software Development: RE: Using dspQDMA library on OMAP-L138
- Hi Mike,
I will check on the initialization value. I was calling the SEM_pend function immediately after requesting the DMA operation initially so that I wouldn't leave the routine before the transfer had completed. The last question wa...
10/19/2011
- MW 12:38 PM Software Development: RE: Using dspQDMA library on OMAP-L138
- Hi Richard,
How are you creating the Semaphore? Zero initialization value?
Is it possible your routine that is pending is running slower than the 5 ms PRD timer (and you are effectively falling behind)? Are your timer routines ru... - I am using the dspQDMA class in a project on the mity-omap processor. I was able to successfully load all of the components and successfully link my project for the dsp. When I execute the dspQDMA->ReadFromFIFO routine (I am reading data...
10/12/2011
- MW 04:01 PM Software Development: RE: HelloWorldDSP.out syntax error
- Hi Peter,
Thank you for your feedback. We'll try to update the Hello World page and address your comments. The challenge of course is that many tools (e.g., CCS from TI and eclipse in general) continue to migrate and change and we m... - PS 03:19 PM Software Development: Reflections after building DSP "Hello, world!"
- I managed to compile the DSP Hello World...*finally*.
(Using Version: 4.2.4.00033 of CCS on WinXP)
I noticed a few of issues when following the guide at:
http://support.criticallink.com/redmine/projects/arm9-platforms/wiki/DSP_Hel... - Hello,
We are trying to debug a uPP application and routed the chan A and Chan B signals through the fpga to connector J104. The Industrial IO data sheet lists 10 of these pins as LVDS pairs and mentions added termination resistors f...
10/10/2011
- MC 03:36 PM Software Development: RE: HelloWorldDSP.out syntax error
- those binaries were a great sanity check for me. you guys might consider posting them to the quick start page.
Mike
10/06/2011
- Hi,
After transferring the jffs2 filesystem via uBoot, using the "nand write.jffs2 C2000000 0 <>" command, is there any method to check whether the file system is fine - before starting kernel - in order to detect block errors or possi...
10/03/2011
- SW 03:48 PM Software Development: RE: uPP digital loopback
- Greg,
I'm using the default ASYNCH3 clock which is PLL_SYSCLK1 I think. This should be divided down automatically. Since I am just using this to test the uPP I won't worry about it and keep the Chan A and Chan B clock divisors equal... - GG 01:49 PM Software Development: RE: uPP digital loopback
- Hi Scott,
As far as I know we have not seen any issue like what you're describing when using a uPP clock driven by the FPGA. Given, we haven't done much work with the uPP in DLB, so it could be a problem unique to that setup.
Anoth... - Hello,
I have a linux driver module to test the uPP in digital loopback. I saw some odd behavior in regards to the clock divisors on Channels A and B. I have the module set to loopback 64 bytes from channel A to channel B. If I se...
09/30/2011
- ME 06:30 AM Software Development: RE: Additional serial port on the MityDSP Profibus dev-kit
- Just thought I'd add a note in case some one else stumbles upon this thread:
Ended up using a Prolific usb-to-serial device that was laying around the office.
I had to build a new kernel with support for usb-to-serial devices and th...
09/29/2011
- Are there test points available on the MityDSP-L138F for the following uPP signals?
'UPP_CHA_ENABLE' = L138 Pin#U16 to FPGA Pin#H5
'UPP_CHA_START' = L138 Pin#W15 to FPGA Pin#C1
'UPP_CHA_CLOCK' = L138 Pin#U17 to FPGA Pin#H7
Than... - SW 10:40 AM Software Development: RE: upp clock
- Greg,
Thanks for the reply. My question was more of how the clocks are setup on the board as a default. I suspected that the clocks were standard with the the uPP xmit clock 300/4 MHz. I found my problem with the uPP code in the en... - ME 08:30 AM Software Development: RE: Additional serial port on the MityDSP Profibus dev-kit
- No, I don't think ssh would work. It has to be something I could open and interact with just like a com port from my code, I'm not sure you can do that with ssh? Either way the recieving end is a windows box and it seems unlikely there w...
- MW 08:18 AM Software Development: RE: Additional serial port on the MityDSP Profibus dev-kit
- (re: comm over ethernet)
Is ssh acceptable? "ssh root@mitydspaddr"
-Mike
- MW 08:17 AM Software Development: RE: Additional serial port on the MityDSP Profibus dev-kit
- The default kernel and root filesystem may "just work". If you plug in the device you should see some messages about it and the device should appear as /dev/ttyUSB0. If that doesn't happen, then you'll need to run make menuconfig and a...
- ME 08:13 AM Software Development: RE: Additional serial port on the MityDSP Profibus dev-kit
- Hmm, I don't really need a physical port. Is there any com over ethernet software availible for these systems?
/ Mattias - ME 08:10 AM Software Development: RE: Additional serial port on the MityDSP Profibus dev-kit
- Thanks for the speedy reply!
One extra port should suffice. I'll order one of the keyspan adapters right away.
I'm using the MityDSP-L138 SoM. Can you point me in the right direction for properly configuring the kernel?
I guess i... - MW 07:49 AM Software Development: RE: Additional serial port on the MityDSP Profibus dev-kit
- Hi Mattias,
I think that your best (or easiest) bet would be to use a usb-to-serial adapter on the Host (USB1) port. If you need more than one, you should be able to use a (powered) hub and attach multiple units. We have used Keyspa... - Hi, I'm wondering what the best way to get an additional serial port is? Is there support for usb-to-serial adapters?
I'm developing something that will need to have both serial, profibus and ethernet support for data transfer and wi...
09/28/2011
- GG 04:35 PM Software Development: RE: upp clock
- Hi Scott,
The fastest you will be able to get the uPP transmit clock to run with your setup is 75 MHz.
From the Upp User's Guide:
"The fixed divisor restricts the maximum speed of the I/O clock to one-fourth the device CPU cloc...
09/27/2011
- I have a userspace upp driver that I am trying to test in loopback mode. I am trying to loopback 1 line of a memory buffer (4096 bytes). I am polling the status register and when it catches the status registers for Q and I appear to ha...