Mity CPU Platforms

12/28/2011

TC 08:20 AM MityDSP (TI TMS320C6xxx Based Products) PCB Development: RE: FPGA/DSP Interface Details & external interrupts

Doug -
I will let the technical team answer the question about the external interrupts. However, we will add information in our design guide detailing the interface between the FPGA and DSP, we will get this done as soon as possible.... Thomas Catalino

TC 08:16 AM MityDSP (TI TMS320C6xxx Based Products) PCB Development: FPGA/DSP Interface Details & external interrupts

(Posted on behalf of a customer)
I am working on designing the carrier interface board for the MityDSP Pro module. I have the carrier design guideline document but I would like to get more details on the DSP board itself. Specifically... Thomas Catalino

12/23/2011

MW 09:45 AM MityDSP (TI TMS320C6xxx Based Products) PCB Development: RE: MityDSP-Pro FPGA questions ...

> In the directory labeled “C:\MityDSP\2.10\hardware\FPGA_boot” I see several sub directories that appear to have pre-compiled FPGA bitstreams for various sized FPGA’s of which I am very familiar with having designed with Xilinx for over... Michael Williamson

12/22/2011

TC 11:53 AM MityDSP (TI TMS320C6xxx Based Products) PCB Development: RE: MityDSP-Pro FPGA questions ...

(from Anthony)
Michael,

Thanks for the response. From what you describe it seems that the signals I intend to use are fine the way they are connected up in our schematics, which just leaves us needing to make sure we have the boo... Thomas Catalino

12/21/2011

MW 07:16 PM MityDSP (TI TMS320C6xxx Based Products) PCB Development: RE: MityDSP-Pro FPGA questions ...

Hi Tom / Anthony,
I hope this doesn't muddy the waters, but here is some more information: There are actually 3 EMAC interface options available for the MityDSP-PRO module. DSP using 10/100 MII, DSP using Reduced Gigabit MII, and FP... Michael Williamson

TC 01:01 PM MityDSP (TI TMS320C6xxx Based Products) PCB Development: RE: MityDSP-Pro FPGA questions ...

??From the schematics it appears that the evaluation board is connected to both RJ-45 connectors, one goes to the 10/100 signals on the plug-in module DSP EMAC and the other to what appears to be a Gigabit PHY which uses a GEMAC running ... Thomas Catalino

AM 11:04 AM MityDSP (TI TMS320C6xxx Based Products) PCB Development: RE: MityDSP-Pro FPGA questions ...

Hello Tom,
I will try posting this to the support forum as well but I need to clear up some confusion Kevin and I were having yesterday as to what we were seeing. But I need to ask some questions to make sure I understand myself what ... Anthony Medina

12/20/2011

JP 12:11 PM ARM9 Based QNX Platforms Software Development: RE: SPI clock polarity

It looks like the spi driver does not do anything with the SPI_MODE_CKPOL_HIGH flag you are trying to use.
I haven't tried this with an actual device, but this is my guess on how to fix this. In the file named:
bsp-mitydsp-omap-l13... John Pruitt

JP 12:09 PM ARM9 Based QNX Platforms Software Development: SPI clock polarity

Question received outside of Redmine:
I am trying to interface a SPI device to the MightDSP board. The clock requirement for this device is that the clock polarity should be high, that is normally high when not being asserted. I hav... John Pruitt

12/15/2011

MW 02:35 PM MityDSP (TI TMS320C6xxx Based Products) PCB Development: RE: MityDSP-Pro FPGA questions ...

The bootloader FPGA image included in the file mention provides a basic UART at pins 14 and 16 of the edge connector as you mentioned.
The FPGA_RSV1 and FPGA_RSV2 lines are not driven, unfortunately. They were left floating in the bo... Michael Williamson

12/14/2011

TC 06:13 PM MityDSP (TI TMS320C6xxx Based Products) PCB Development: MityDSP-Pro FPGA questions ...

(posted on behalf of a customer)
RS232_TXD SO-DIMM pin 14
RS232_RXD SO-DIMM pin 16

FPGA_RSV1 SO-DIMM pin 21
FPGA_RSV2 SO-DIMM pin 23

Since we are not using anything out of the F... Thomas Catalino

12/09/2011

ME 08:57 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Using the EMIFA interface on the Mitydsp-1810

We changed chip select to CS4 and kept having the same issues. We've done some other measurements and tests and we now doubt it's some kind of contention, it is most likely some problem on the ASIC side rather than the arm side of things... Mattias Ekstrom

MW 07:39 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Using the EMIFA interface on the Mitydsp-1810

Hi Mattias,
The only chip select used on the EMIFA by default is CS3 (used for the NAND). Our FPGA driver framework uses CS5, but if you don't load the modules for the drivers (e.g., fpga_ctrl.ko) then that CS should not be used duri... Michael Williamson

ME 03:58 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Using the EMIFA interface on the Mitydsp-1810

Hi,
I was wondering which chip selects are unused by default? What I can see in the u-boot and linux source is that only CS2 and CS3 are used. We're using chip select 5 right now but we're having some issues and I'm not sure what's ca... Mattias Ekstrom

12/07/2011

SW 04:37 PM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: FPGA load causes reboot

Mike,
Your .bin file loaded up fine. I had the designer look at the build, and he had some IO not constrained corectly. I think it might have been to the EMIFA interface. He has fixed that and I was able to load up the build and acce... Scott Whitney

MW 09:38 AM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: FPGA load causes reboot

Scott,
My suspicion is that the pins tied to the EMIFA (a chip select line, a wait line, or perhaps the data lines) are being driving when they shouldn't be. I would double check your bitstream configuration options for unused IOBs, ... Michael Williamson

12/06/2011

SW 03:43 PM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: FPGA load causes reboot

Mike,
The arm is idle when it dies. I will post some captured text. It looks like it can't access the flash memory. We are downloading via jtag. Scott Whitney

MW 03:27 PM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: FPGA load causes reboot

Can you post what the ARM console sees when it crashes? You are downloading via JTAG, correct?
Is the ARM running the UPP when it dies, or is the FPGA basically idle?
-Mike
Michael Williamson

SW 03:15 PM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: FPGA load causes reboot

Mike,
I had our fpga designer rebuild our smaller (uPP interface) build that we were running the lx16 and retarget it for the xl45. It was able to download the design successfully, but very shortly afterwords the ARM crashes. Scott Whitney

SW 01:14 PM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: FPGA load causes reboot

Mike,
Thanks for the quick reply. this is the only lx45 board in house now. I think we are expecting a few more to come in shortly. This is a new design. We have an lx16 and our designer took this design and stripped most of it out ... Scott Whitney

MW 01:04 PM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: FPGA load causes reboot

Hi Scott,
Have you confirmed your image works on other MityDSP-L138F with lx56 FPGA modules or is this a new FPGA design? If it is the former, we can send some test .bit images to confirm a hardware problem. If it is the latter, you... Michael Williamson

SW 12:58 PM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: FPGA load causes reboot

Hello,
We just got a new mityDSP l138 with the lx45 FPGA. When I try downloading my fpga build via jtag it fails. I get a Programming terminated DONE did not go high error in impact. When this happens the ARM reboots. Any ideas on t... Scott Whitney